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| ISP1362 Single-chip Universal Serial Bus On-The-Go controller Rev. 03 -- 06 January 2004 Product data 1. General description The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller integrated with the advanced Philips Slave Host Controller (PSHC) and the Philips ISP1181B Device Controller (DC). The USB OTG controller is compliant with On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a. The host and device controllers are compliant with Universal Serial Bus Specification Rev. 2.0, supporting data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s). The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be hardware configured to function as a downstream port, an upstream port or an OTG port whereas port 2 can only be used as a downstream port. The OTG port can switch roles from host to peripheral, or from peripheral to host. The OTG port can become a host through the Host Negotiation Protocol (HNP) as specified in the OTG supplement. A USB product with OTG capability can function either as a host or as a peripheral. For instance, with this dual-role capability, a Personal Computer (PC) peripheral such as a printer may switch roles from a peripheral to a host for connecting to a digital camera so that the printer can print pictures taken by the camera without using a PC. When a USB product with OTG capability is inactive, the USB interface is turned off. This feature has made OTG a technology well-suited for use in portable devices--such as, Personal Digital Assistant (PDA), Digital Still Camera (DSC) and mobile phone--in which power consumption is a concern. The ISP1362 is an OTG controller designed to perform such functions. 2. Features s Complies fully with: x Universal Serial Bus Specification Rev. 2.0 x On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a s Supports data transfer at full-speed (12 Mbit/s) and low-speed (1.5 Mbit/s) s Adapted from Open Host Controller Interface Specification for USB Release 1.0a s USB OTG: x Supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for OTG dual-role devices x Provides status and control signals for software implementation of HNP and SRP x Provides programmable timers required for HNP and SRP x Supports built-in and external source of VBUS x Output current of the built-in charge pump is adjustable by using an external capacitor Philips Semiconductors ISP1362 Single-chip USB OTG controller s s s s s s s s s s s s s s s USB host: x Supports integrated physical 4096 bytes of multiconfiguration memory x Supports all four types of USB transfers: control, bulk, interrupt and isochronous x Supports multiframe buffering for isochronous transfer x Supports automatic interrupt polling rate mechanism x Supports paired buffering for bulk transfer x Directly addressable memory architecture; memory can be updated on-the-fly USB device: x Supports high performance USB interface device with integrated Serial Interface Engine (SIE), buffer memory and transceiver x Supports fully autonomous and multiconfiguration DMA operation x Supports up to 14 programmable USB endpoints with 2 fixed control IN/OUT endpoints x Supports integrated physical 2462 bytes of multiconfiguration memory x Supports endpoints with double buffering to increase throughput and ease real-time data transfer x Supports controllable LazyClock (110 kHz 50 %) output during `suspend' Supports two USB ports: port 1 and port 2 x Port 1 can be configured to function as a downstream port, an upstream port or an OTG port x Port 2 can be used only as a downstream port Supports software-controlled connection to the USB bus (SoftConnectTM) Supports good USB connection indicator that blinks with traffic (GoodLinkTM) Complies with USB power management requirements Supports internal power-on and low-voltage reset circuit, with possibility of a software reset Supports operation over the extended USB voltage range (4.0 V to 5.5 V) with 5 V tolerant I/O pads High-speed parallel interface to most CPUs available in the market, such as Hitachi SH-3, Intel(R) StrongARM(R), Philips XA, Fujitsu SPARClite(R), NEC and Toshiba MIPS, ARM7/9, Motorola DragonBallTM and PowerPCTM Reduced Instruction Set Computer (RISC): x 16-bit data bus x 10 Mbyte/s data transfer rate between the microprocessor and ISP1362 Supports Programmed I/O (PIO) or Direct Memory Access (DMA) Supports `suspend' and remote wake-up Uses 12 MHz crystal or direct clock source with on-chip Phase-Locked Loop (PLL) for low Electro-Magnetic Interference (EMI) Operates at +3.3 V power supply Operating temperature range from -40 C to +85 C Available in 64-pin LQFP and TFBGA packages. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 2 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 3. Applications The ISP1362 can be used to implement a dual-role USB device in any application--USB host or USB peripheral--depending on the cable connection. If the dual-role device is connected to a typical USB peripheral, it behaves like a typical USB host. The dual-role device, however, can also be connected to a PC or any other USB host and behave like a typical USB peripheral. 3.1 Host/peripheral roles s Mobile phone to/from: x Mobile phone: exchange contact information x Digital still camera: e-mail pictures or upload pictures to the web x MP3 player: upload, download and broadcast music x Mass storage: upload and download files x Scanner: scan business cards s Digital still camera to/from: x Digital still camera: exchange pictures x Mobile phone: e-mail pictures, upload pictures to the web x Printer: print pictures x Mass storage: store pictures s Printer to/from: x Digital still camera: print pictures x Scanner: print scanned image x Mass storage: print files stored in a device s MP3 player to/from: x MP3 player: exchange songs x Mass storage: upload and download songs s Oscilloscope to/from: x Printer: print screen image s Personal digital assistant to/from: x Personal digital assistant: exchange files x Printer: print files x Mobile phone: upload and download files x MP3 player: upload and download songs x Scanner: scan pictures x Mass storage: upload and download files x Global Positioning System (GPS): obtain directions, mapping information x Digital still camera: upload pictures x Oscilloscope: configure oscilloscope. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 3 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 4. Abbreviations DC -- Device Controller DMA -- Direct Memory Access DSC -- Digital Still Camera EMI -- Electro-Magnetic Interference GPS -- Global Positioning System HC -- Host Controller HCD -- Host Controller Driver HNP -- Host Negotiation Protocol OTG -- On-The-Go PDA -- Personal Digital Assistant PIO -- Programmed Input/Output PLL -- Phase-Locked Loop PSHC -- Philips Slave Host Controller SIE -- Serial Interface Engine SRP -- Session Request Protocol USB -- Universal Serial Bus. 5. Ordering information Table 1: Ordering information Package Name ISP1362BD ISP1362EE ISP1362EE/01 LQFP64 TFBGA64 Description plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm Version SOT314-2 Type number plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm SOT543-1 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 4 of 150 xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x Product data Rev. 03 -- 06 January 2004 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 6. Block diagram Philips Semiconductors 12 MHz X2 44 RESET H_SUSPEND/ H_WAKEUP 32 POWER-ON RESET internal reset HC BUFFER MEMORY PLL CLKOUT X1 43 38 ISP1362 33 2, 3, 5 to 8, 10 to 13, 15 to 18, 63, 64 20 21 22 61 62 28 29 24 25 30 31 23 59 60 to system clock ADVANCED PHILIPS SLAVE HOST CONTROLLER OVERCURRENT PROTECTION 56 35 36 42 41 46 47 VDD_5V H_PSW1 H_PSW2 H_OC1 H_OC2 H_DM2 H_DP2 16 D0 to D15 RD CS WR A0 A1 DACK1 DACK2 DREQ1 DREQ2 INT1 INT2 TEST0 TEST1 TEST2 BUS INTERFACE ON-THE-GO CONTROLLER USB TRANSCEIVER OTG TRANSCEIVER PHILIPS DEVICE CONTROLLER CHARGE PUMP 49 50 OTG_DM1 OTG_DP1 55 VBUS DC BUFFER MEMORY 1, 9, 19, 27, 37, 57 51 4, 14, 26, 40, 52, 58 34 GOODLINK 39 45 48 54 53 Single-chip USB OTG controller 004aaa044 DGND AGND VCC D_SUSPEND/ D_WAKEUP GL ID OTGMODE CP_CAP2 CP_CAP1 ISP1362 5 of 150 Fig 1. Block diagram. Philips Semiconductors ISP1362 Single-chip USB OTG controller 7. Pinning information 7.1 Pinning 49 OTG_DM1 48 ID 47 H_DP2 46 H_DM2 45 OTGMODE 44 X2 43 X1 42 H_OC1 41 H_OC2 40 VCC 39 GL 38 CLKOUT 37 DGND 36 H_PSW2 35 H_PSW1 34 D_SUSPEND/D_WAKEUP 33 H_SUSPEND/H_WAKEUP D14 17 D15 18 DGND 19 RD 20 CS 21 WR 22 TEST0 23 DREQ1 24 DREQ2 25 VCC 26 DGND 27 DACK1 28 DACK2 29 INT1 30 INT2 31 RESET 32 004aaa050 DGND 1 D2 2 D3 3 VCC 4 D4 5 D5 6 D6 7 D7 8 ISP1362BD DGND 9 D8 10 D9 11 D10 12 D11 13 VCC 14 D12 15 D13 16 Fig 2. Pin configuration LQFP64. 50 OTG_DP1 54 CP_CAP2 53 CP_CAP1 56 VDD_5V 60 TEST2 59 TEST1 57 DGND 51 AGND 55 VBUS 58 VCC 52 VCC 64 D1 63 D0 62 A1 61 A0 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 6 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 004aaa151 K J H G F E D C B A 1 ball A1 index area 2 3 4 5 6 7 8 9 10 ISP1362EE ISP1362EE/01 Fig 3. Pin configuration TFBGA64. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 7 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 7.2 Pin description Table 2: Symbol[1] DGND D2 Pin description Pin LQFP64 1 2 Ball TFBGA64 B1 C2 Type[2] I/O Description digital ground bit 2 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D3 3 C1 I/O bit 3 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output VCC D4 4 5 D2 D1 I/O supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 F bit 4 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D5 6 E2 I/O bit 5 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D6 7 E1 I/O bit 6 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D7 8 F2 I/O bit 7 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output DGND D8 9 10 F1 G2 I/O digital ground bit 8 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D9 11 G1 I/O bit 9 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D10 12 H2 I/O bit 10 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D11 13 H1 I/O bit 11 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 8 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 2: Symbol[1] VCC D12 Pin description...continued Pin LQFP64 14 15 Ball TFBGA64 J2 J1 Type[2] I/O Description supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 F bit 12 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output bit 13 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output bit 14 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output bit 15 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output digital ground read strobe input; when asserted LOW, it indicates that the HC/DC driver is requesting a read to the buffer memory or the internal registers of the HC/DC input with hysteresis chip select input (active LOW); enables the HC/DC driver to access the buffer memory and registers of the HC/DC input write strobe input; when asserted LOW, it indicates that the HC/DC driver is requesting a write to the buffer memory or the internal registers of the HC/DC input with hysteresis for test input and output; pulled HIGH by a 100 k resistor bidirectional, push-pull input, three-state output DMA request output; when active, it signals the DMA controller that a data transfer is requested by the HC; the active level (HIGH or LOW) of the request is programmed by using the HcHardwareConfiguration register (20H/A0H) If the OneDMA bit of the HcHardwareConfiguration register is set to logic 1, both the HC and DC DMA channel will be routed to DREQ1 and DACK1. push-pull output D13 16 K1 I/O D14 17 K2 I/O D15 18 J3 I/O DGND RD 19 20 K3 J4 I CS 21 K4 I WR 22 J5 I TEST0 DREQ1 23 24 K5 J6 I/O O DREQ2 25 K6 O DMA request output; when active, it signals the DMA controller that a data transfer is requested by the DC; the active level (HIGH or LOW) of the request is programmed by using the DcHardwareConfiguration register (BAH/BBH) push-pull output 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 9 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 2: Symbol[1] VCC DGND DACK1 Pin description...continued Pin LQFP64 26 27 28 Ball TFBGA64 J7 K7 J8 Type[2] I Description supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 F digital ground DMA acknowledge input; indicates that a request for DMA transfer from the HC has been granted by the DMA controller; the active level (HIGH or LOW) of the acknowledge signal is programmed by using the HcHardwareConfiguration register (20H/A0H); when not in use, this pin must be connected to VCC through a 10 k resistor input with hysteresis DMA acknowledge input; indicates that a request for DMA transfer from the DC has been granted by the DMA controller; the active level (HIGH or LOW) of the acknowledge signal is programmed by using the DcHardwareConfiguration register (BAH/BBH); when not in use, this pin must be connected to VCC through a 10 k resistor input with hysteresis interrupt request from the HC; provides a mechanism for the HC to interrupt the microprocessor; see HcHardwareConfiguration register (20H/A0H) Section 15.4.1 for details If the OneINT bit of the HcHardwareConfiguration register is set to logic 1, both the HC and DC interrupt request will be routed to INT1. push-pull output DACK2 29 K8 I INT1 30 J9 O INT2 31 K9 O interrupt request from the DC; provides a mechanism for the DC to interrupt the microprocessor; see DcHardwareConfiguration register (BAH/BBH) Section 16.1.4 for details push-pull output reset input input with hysteresis and internal pull-up resistor I/O pin (open-drain); goes HIGH when the HC is in the `suspend' mode; a LOW pulse must be applied to this pin to wake up the HC; connect a 100 k resistor to VCC bidirectional, push-pull input, three-state open-drain output I/O pin (open-drain); goes HIGH when the DC is in the `suspend' mode; a LOW pulse must be applied to this pin to wake up the DC; connect a 100 k resistor to VCC bidirectional, push-pull input, three-state open-drain output connects to the external PMOS switch; required when the external charge pump or external VBUS is used for providing VBUS to the downstream port LOW -- switches ON the PMOS providing VBUS to the downstream port HIGH -- switches OFF the PMOS when not in use, leave this pin open open-drain output RESET H_SUSPEND/ H_WAKEUP 32 33 K10 J10 I I/O D_SUSPEND/ D_WAKEUP 34 H9 I/O H_PSW1 35 H10 O 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 10 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 2: Symbol[1] H_PSW2 Pin description...continued Pin LQFP64 36 Ball TFBGA64 G9 Type[2] O Description connects to the external PMOS switch LOW -- switches ON the PMOS providing VBUS to the downstream port HIGH -- switches OFF the PMOS when not in use, leave this pin open open-drain output DGND CLKOUT 37 38 G10 F9 O digital ground programmable clock output; the default clock frequency is 12 MHz and can be varied from 3 MHz to 48 MHz push-pull output GoodLink LED indicator output; the LED is OFF by default, blinks ON upon USB traffic open-drain output; 4 mA supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 F overcurrent sense input for downstream port 2; both the digital and analog overcurrent inputs can be used for port 2, depending on the hardware mode register setting; when not in use, it is recommended to connect this pin to the VDD_5V pin overcurrent sensing input for downstream port 1; both the digital and analog overcurrent inputs can be used for port 1, depending on the hardware mode register setting; when not in use, it is recommended to connect this pin to the VDD_5V pin crystal input; connected directly to a 12 MHz crystal; when this pin is connected to an external clock oscillator, leave pin X2 open crystal output; connected directly to a 12 MHz crystal; when pin X1 is connected to an external clock oscillator, leave this pin open to select whether port 1 is operating in the OTG or non-OTG mode; see Table 8 input with hysteresis downstream D- signal; host only, port 2; when not in use, leave this pin open and set bit ConnectPullDown_DS2 of the HcHardwareConfiguration register downstream D+ signal; host only, port 2; when not in use, leave this pin open and set bit ConnectPullDown_DS2 of the HcHardwareConfiguration register input pin for sensing OTG ID; the status of this input pin is reflected in the OTGStatus register (bit 0); see Table 8 input with hysteresis D- signal of the OTG port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3] D+ signal of the OTG port, the downstream host port 1 or the upstream device port; when not in use, leave this pin open and set bit ConnectPullDown_DS1 of the HcHardwareConfiguration register[3] (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. GL 39 F10 O VCC H_OC2 40 41 E9 E10 I H_OC1 42 D9 I X1 X2 OTGMODE 43 44 45 D10 C9 C10 AI AO I H_DM2 46 B9 AI/O H_DP2 47 B10 AI/O ID 48 A10 I OTG_DM1 49 A9 AI/O OTG_DP1 50 B8 AI/O 9397 750 12337 Product data Rev. 03 -- 06 January 2004 11 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 2: Symbol[1] AGND VCC CP_CAP1 CP_CAP2 VBUS Pin description...continued Pin LQFP64 51 52 53 54 55 Ball TFBGA64 A8 B7 A7 B6 A6 Type[2] AI/O AI/O I/O Description analog ground; used for OTG ATX supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 F charge pump capacitor pin 1; low ESR; see Section 11.6 charge pump capacitor pin 2; low ESR; see Section 11.6 analog input and output OTG mode -- built-in charge pump output or VBUS voltage comparators input; connect to pin VBUS of the OTG connector DC mode -- input as VBUS sensing; connect to pin VBUS of the upstream connector HC mode -- not used; leave open VDD_5V 56 B5 I supply reference voltage (5 V); to be used together with built-in overcurrent circuit; when built-in overcurrent circuit is not in use, this pin can be tied to VCC; it is recommended to connect a decoupling capacitor of 0.01 F digital ground supply voltage (3.3 V); it is recommended to connect a decoupling capacitor of 0.01 F for test input and output, pulled to GND by a 10 k resistor bidirectional, push-pull input, three-state output for test input and output, pulled to GND by a 10 k resistor bidirectional, push-pull input, three-state output command or data phase input LOW -- PIO bus of the HC is selected HIGH -- PIO bus of the DC is selected input DGND VCC TEST1 TEST2 A0 A1 57 58 59 60 61 62 A5 B4 A4 B3 A3 B2 I/O I/O I I D0 63 A2 I/O bit 0 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output bit 1 of the bidirectional data bus that connects to the internal registers and buffer memory of the ISP1362; the bus is in the high-impedance state when it is idle bidirectional, push-pull input, three-state output D1 64 A1 I/O [1] [2] [3] Symbol names with an overscore (for example, NAME) represent active LOW signals. All I/O pads are 5 V tolerant. In the OTG mode, this pin is pulled down by an internal resistor. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 12 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 8. Functional description 8.1 On-The-Go (OTG) controller The OTG Controller provides all the control, monitoring and switching functions required in OTG operations. 8.2 Advanced Philips Slave Host Controller (PSHC) The advanced Philips Slave HC is designed for highly optimized USB host functionality. Many advanced features are integrated to fully utilize the USB bandwidth. A number of tasks are performed at the hardware level. This reduces the requirement on the microprocessor and thus speeds up the system. 8.3 Philips Device Controller (DC) The Philips DC is a high performance USB device with up to 14 programmable endpoints. These endpoints can be configured as double-buffered endpoints to further enhance the throughput. 8.4 Phase-Locked Loop (PLL) clock multiplier A 12 MHz-to-48 MHz clock multiplier PLL is integrated on-chip. This allows the use of a low-cost 12 MHz crystal that also minimizes Electro-Magnetic Interference (EMI) because of low frequency. No external components are required for the operation of PLL. 8.5 USB and OTG transceivers The integrated transceivers (for typical downstream port) directly interface to the USB connectors (type A) and cables through some termination resistors. The transceiver is compliant with Universal Serial Bus Specification Rev 2.0. 8.6 Overcurrent protection The ISP1362 has a built-in overcurrent protection circuitry. This feature monitors the current drawn on the downstream VBUS and switches off VBUS when the current exceeds the current threshold. The built-in overcurrent protection feature can be used when the port acts as a host port. 8.7 Bus interface The bus interface connects the microprocessor to the USB host and the USB device allowing fast and easy access to both. 8.8 DC and HC buffer memory 4096 bytes (host) and 2462 bytes (device) of built-in memory provide sufficient space for the buffering of USB traffic. Memory in the HC is addressable by using the fast and versatile direct addressing method. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 13 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 8.9 GoodLink Indication of a good USB connection is provided through the GoodLink technology (open-drain, maximum current: 4 mA). During enumeration, LED indicators blink ON momentarily corresponding to the enumeration traffic of the ISP1362 ports. The LED also blinks ON whenever there is valid traffic to the USB ports. In the `suspend' mode, the LED is OFF. This feature of GoodLink provides a user-friendly indication on the status of the USB traffic between the host and the hub, as well as the connected devices. It is a useful diagnostics tool to isolate faulty equipment and helps to reduce field support and hotline costs. 8.10 Charge pump The charge pump generates a 5 V supply from 3.3 V to drive VBUS when the ISP1362 is an A-device in the OTG mode. For details, see Section 11.6. 9. Host and device bus interface The interface between the external microprocessor and the ISP1362 Host Controller (HC) and Device Controller (DC) is separately handled by the individual bus interface circuitry. The host or device automux selects the path for the host access or the device access. This selection is determined by the A1 address line. For any access to HC or DC registers, the command phase and the data phase are needed, which is determined by the A0 address line. All the functionality of the ISP1362 can be accessed using a group of registers and two buffer memory areas (one for the HC and the other the DC). Registers can be accessed using the Programmed I/O (PIO) mode. The buffer memory can be accessed using both the PIO and direct memory access (DMA) modes. When CS is LOW (active), the address pin A1 has priority over DREQ and DACK. Therefore, as long as the CS pin is held LOW, the ISP1362 bus interface does not respond to any DACK signals. When CS is HIGH (inactive), the bus interface will respond to DREQn and DACKn. The address pin A1 will be ignored when CS is inactive. An active DACKn signal when the DREQn is inactive will be ignored. If DREQ1, DACK1, DREQ2 and DACK2 are active, the bus interface will be switched off to avoid potential data corruption. Table 3 provides the bus access priority for the ISP1362. Table 3: 1 2 3 4 5 [1] 9397 750 12337 Bus access priority table for the ISP1362 A1 L H X X X DACK1 X X L X X DACK2 X X X L X DREQ1 DREQ2 HC and DC active X X H L H X X L H H HC DC HC[1] DC[1] no driving L L H H H Priority CS Only for enabling of the bus and disabling of the bus. Depends only on the DACK signal. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 14 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 9.1 Memory organization The buffer memory in the HC uses a multiconfigurable direct addressing architecture. The 4096 bytes HC buffer memory is shared by the ISTL0, ISTL1, INTL and ATL buffers. ISTL0 and ISTL1 are used for isochronous traffic (double buffer), INTL is used for interrupt traffic, and ATL is used for control and bulk traffic. The allocation of the buffer memory follows the sequence ISTL0, ISTL1, INTL, ATL and unused memory. For example, consider that the buffer sizes of the ISTL, INTL and ATL buffers are 1024 bytes, 1024 bytes and 1024 bytes, respectively. Then, ISTL0 will start from memory location 0, ISTL1 will start from memory location 1024 (size of ISTL0), INTL will start from memory location 2048 (size of ISTL0 + size of ISTL1) and ATL will start from memory location 3072 (size of ISTL0 + size of ISTL1 + size of INTL). The HCD has the responsibility to ensure that the sum of the four memory buffers does not exceed the total memory size. If this condition is violated, it will lead to data corruption. The buffer size must be a multiple of two bytes (one word). The buffer memory of the DC follows a similar architecture. Details on the DC memory area allocation can be found in Section 13.3. Note that the DC buffer memory does not support the direct addressing mode. 9.1.1 Memory organization for the HC The HC in the ISP1362 has a total of 4096 bytes of buffer memory. This buffer area is divided into four parts (see Table 4 and Figure 4): Table 4: Buffer memory areas and their applications Application isochronous transfer (double buffering) interrupt transfer control and bulk transfer Buffer memory area ISTL0 and ISTL1 INTL ATL The ISTL0 and ISTL1 buffers must have the same size. Memory is allocated by the HC according to the value set by the HCD in HcISTLBufferSize, HcINTLBufferSize and HcATLBufferSize. All buffer sizes must be multiples of two bytes (one word). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 15 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 0x0000 ISTL0 area (512 bytes) 0x03FF 0x0400 ISTL1 area (512 bytes) 0x07FF 0x0800 INTL area (512 bytes) 0x09FF 0x0A00 ATL area (1536 bytes) 0x0FFF 004aaa053 Fig 4. Recommended values of the ISP1362 buffer memory allocation. The INTL and ATL buffers use `blocked memory management' scheme to enhance the status and control capability of each and every individual PTD structure. The INTL and ATL buffers are further divided into blocks of equal sizes depending on the value written to the HcATLBlkSize register (ATL) and the HcINTLBlkSize register (INTL). The ISP1362 HC supports up to 32 blocks in the ATL and INTL buffers. Each of these blocks can be used for one complete Philips Transfer Descriptor (PTD) data. Note that the block size does not include the 8-byte PTD header and is strictly the size of the payload. Both the ATL and INTL block sizes must be a multiple of DWord (4 bytes). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 16 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Starting address of the ATL or INTL buffer area 8 bytes PTD header Block of 72 bytes (64 + 8, where 64 is the block size defined) 64 bytes PTD header Payload area 8 bytes PTD header 64 bytes PTD header Payload area 72 bytes 8 bytes PTD header 72 bytes 64 bytes PTD header Payload area 004aaa055 Fig 5. A sample snapshot of the ATL or INTL memory management scheme. Figure 5 provides a snapshot of a sample ATL or INTL buffer area of 256 bytes with a block size of 64 bytes. The HCD may put a PTD with payload size of up to 64 bytes but not more. Depending on the ATL or INTL buffer size, up to 32 ATL blocks and 32 INTL blocks can be allocated. Note that a portion of the ATL or INTL buffer remains unused. This is allowed but can be avoided by choosing the appropriate ATL or INTL buffer size and block size. The ISTL0 or ISTL1 buffer memory (for isochronous transfer) uses a different memory management scheme (see Figure 6). There is no fixed block size for the ISTL buffer memory. While the PTD header remains 8 bytes for all PTDs, the PTD payload can be of any size. The PTD payload, however, is padded to the next DWord boundary when the HC calculates the location of the next PTD header. The ISP1362 HC checks the payload size from the `Total size' field of the PTD itself and calculates the location of the next PTD header based on this information. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 17 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Starting address of ISTL0 or ISTL1 PTD header (Total size = 64) 72 bytes (64 + 8) PTD payload (64 bytes) PTD header (Total size = 160) 168 bytes (160 + 8) PTD payload (160 bytes) PTD header (Total size = 32) PTD payload (32 bytes) 40 bytes (32 + 8) 004aaa054 `Total size' is a 10-bit field in the PTD. Fig 6. A sample snapshot of the ISTL memory management scheme. 9.1.2 Memory organization for the DC The ISP1362 DC has a total of 2462 bytes of built-in buffer memory. This buffer memory is multiconfigurable to support the requirements of different applications. The DC buffer memory is divided into 16 areas to be used by control OUT, control IN and 14 programmable endpoints. Figure 7 provides a snapshot of the DC buffer memory. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 18 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Control OUT (64 bytes) Control IN (64 bytes) Endpoint 1 (128 bytes) Endpoint 2 (128 bytes) Endpoint 3 (512 bytes) Endpoint 4 (64 bytes) Endpoint 5 (64 bytes) Endpoint 6 (96 bytes) Endpoint 7 (96 bytes) 004aaa057 Fig 7. DC buffer memory organization. The buffer memory is configured by the DcEndpointConfiguration registers (ECRs). Although the control endpoint has a fixed configuration, all 16 endpoints (control OUT, control IN and 14 programmable endpoints) must be configured before the DC internally allocates the buffer. The 14 programmable endpoints could be programmed into sizes ranging from 16 bytes to 1023 bytes, single or double buffering. The DC buffer memory for each endpoint can be accessed through the DcReadEndpointBuffer and DcWriteEndpointBuffer registers. 9.2 PIO access mode The ISP1362 provides the PIO mode for external microprocessors to access its internal control registers and buffer memory. It occupies only four I/O ports or four memory locations of a microprocessor. An external microprocessor can read or write to the internal control registers and buffer memory of the ISP1362 through the PIO operating mode. Figure 8 shows the PIO interface between a microprocessor and the ISP1362. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 19 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller P bus interface D [15:0] RD WR MICROPROCESSOR CS A2 A1 IRQ1 IRQ2 D [15:0] RD WR CS A1 A0 INT1 INT2 004aaa042 ISP1362 Fig 8. PIO interface between a microprocessor and the ISP1362. 9.3 DMA mode The ISP1362 also provides the DMA mode for external microprocessors to access the internal buffer memory of the ISP1362. The DMA operation enables data to be transferred between the system memory of a microprocessor and the internal buffer memory of the ISP1362. Remark: The DMA operation must be controlled by the DMA controller of the external microprocessor system (master). Figure 9 shows the DMA interface between a microprocessor system and the ISP1362. The ISP1362 provides two DMA channels. The DMA channel 1 (controlled by the DREQ1 and DACK1 signals) is for the DMA transfer between the system memory of a microprocessor and the internal buffer memory of the ISP1362 HC. The DMA channel 2 (controlled by the DREQ2 and DACK2 signals) is for the DMA transfer between the system memory of a microprocessor and the internal buffer memory of the ISP1362 DC. The ISP1362 provides an internal End-Of-Transfer (EOT) signal to terminate the DMA transfer. P bus interface D [15:0] RD WR MICROPROCESSOR DACK1 DREQ1 DACK2 DREQ2 D [15:0] RD WR DACK1 DREQ1 DACK2 DREQ2 ISP1362 004aaa043 Fig 9. DMA interface between a microprocessor and the ISP1362. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 20 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 9.4 PIO access to internal control registers Table 5 shows the I/O port addressing in the ISP1362. The complete I/O port address decoding should combine with the chip select signal (CS) and the address lines (A1 and A0). The direction of access of I/O ports, however, is controlled by the RD and WR signals When RD is LOW, the microprocessor reads data from the data port of the ISP1362 (see Figure 10). When WR is LOW, the microprocessor writes command to the command port or writes data to the data port (see Figure 11). Table 5: CS L L L L L L H H I/O port addressing A1 A0 L H L H Access R/W W R/W W Data bus width 16 bits 16 bits 16 bits 16 bits Description HC data port HC command port DC data port DC command port The register structure in the ISP1362 is a command-data register pair structure. A complete register access needs a command phase followed by a data phase. The command (also named as the index of a register) is used to inform the ISP1362 about the register that will be accessed at the data phase. On the 16-bit data bus of a microprocessor, a command occupies the lower byte and the upper byte is filled with zeros (see Figure 12). For 32-bit registers, the access cycle is shown in Figure 13. It consists of a command phase followed by two data phases. BUS INTERFACE 0 P bus interface Device bus interface 1 A1 Host bus interface 004aaa122 When A1 = L, microprocessor accesses the HC. When A1 = H, microprocessor accesses the DC. Fig 10. Microprocessor access to the HC or the DC. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 21 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller CMD/DATA SWITCH Host or Device bus interface 1 command port data port 0 A0 Commands . . . Control registers Command register 004aaa160 When A0 = L, microprocessor accesses the data port. When A0 = H, microprocessor accesses the command port. Fig 11. Access to internal control registers. Read 16-bit Write16-bit A0/A1 A0/A1 CS CS RD WR D[15:0] D[15:0] 004aaa045 Fig 12. PIO register access. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 22 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Reading from a 16/32-bit register 32-bit access 16-bit access A0/A1 CS RD WR D[15:0] Command phase Data phase Second data phase for 32-bit register Writing to a 16/32-bit register 32-bit access 16-bit access A0/A1 CS RD WR D[15:0] Command phase Data phase Second data phase for 32-bit register 004aaa046 Fig 13. PIO access for a 16 or 32-bit register. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 23 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The following is a sample code for PIO access to internal control registers: unsigned long read_reg32(unsigned char reg_no) { unsigned int result_l,result_h; unsigned long result; outport(hc_com, reg_no); // Command phase result_l=inport(hc_data); // Data phase result_h=inport(hc_data); // Data phase result = result_h; result = result<<16; result = result+result_l; return(result); } void write_reg32(unsigned char reg_no, unsigned long data2write) { unsigned int low_word; unsigned int hi_word; low_word=data2write&0x0000FFFF; hi_word=(data2write&0xFFFF0000)>>16; outport(hc_com,reg_no|0x80); // Command phase outport(hc_data,low_word); // Data phase outport(hc_data,hi_word); // Data phase } unsigned int read_reg16(unsigned char reg_no) { unsigned int result; outport(hc_com, reg_no); // Command phase result=inport(hc_data); // Data phase return(result); } void write_reg16(unsigned char reg_no, unsigned int data2write) { outport(hc_com,reg_no|0x80); // Command phase outport(hc_data,data2write); // Data phase } 9.5 PIO access to the buffer memory The buffer memory in the ISP1362 can be addressed using either the direct addressing method or the indirect addressing method. 9.5.1 PIO access to the buffer memory by using direct addressing This method uses the HcDirectAddressLength register to specify two parameters required to randomly access the ISP1362 buffer memory (total of 4096 bytes). These two parameters are: 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 24 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Starting address -- Location to start writing or reading Data length -- Number of bytes to write or read. The following is a sample code for setting the HcDirectAddressLength register: void Set_DirAddrLen(unsigned int data_length,unsigned int addr) { unsigned long RegData = 0; RegData =(long)(addr&0x7FFF); RegData|=(((long)data_length)<<16); write_reg32(HcDirAddrLen,RegData); } After the proper value is written to the HcDirectAddressLength register, data is accessible from the HcDirectAddressData register (called as HcDirAddr_Port in the following sample code). A sample code for writing word_size bytes of data from *w_ptr to the memory locations of the ISP1362 buffer starting from the address start_addr is as follows: void direct_write(unsigned int *w_ptr,unsigned int start_addr,unsigned int word_size) { unsigned int cnt=0; Set_DirAddrLen(word_size*2,start_addr); outport(hc_com,HcDirAddr_Port|0x80); // hc_com is system address of // HC command port do { outport(hc_data,*(w_ptr+cnt)); // hc_data is system address of // HC data port cnt++; } while(cnt void write_atl(unsigned int *a_ptr, unsigned int word_size) { int cnt; 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 25 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller write_reg16(HcTransferCnt,word_size*2); outport(hc_com,HcATL_Port|0x80); // hc_com is system address of HC // command port cnt=0; do { outport(hc_data,*(a_ptr+cnt)); cnt++; } while(cnt<(word_size)); // hc_data is system address of HC // data port Remark: The HcTransferCounter register counts the number of bytes even though the transfer is in number of words. Therefore, the transfer counter should be set to word_size x 2. Incorrect setting of the HcTransferCounter register may cause the ISP1362 to go into an indeterminate state. The buffer memory access using indirect addressing always starts from the location 0 of each buffer area. Only the front portion of the memory (example: first 64 bytes of a 1024 bytes buffer) can be accessed. Therefore, to access a portion of the memory that does not start from memory location 0, all memory locations before that location must be accessed in a sequential order. The method is similar to the sequential file access method. 9.6 Setting up a DMA transfer The ISP1362 uses two DMA channels to individually serve the HC and the DC. The DMA transfer allows the system CPU to work on other tasks while the DMA controller transfers data to or from the ISP1362. The DMA slave controller, in the ISP1362, is compatible with the 8327 type DMA controller. The DMA transfer can be used with the direct addressing mode or the indirect addressing mode. The registers used in these two modes are shown in Table 6. Table 6: Registers used in addressing modes HcDMAConfiguration bit[3:1] 1XXB 0XXB Total bytes to transfer HcDirectAddressLength HcTransferCounter Addressing mode[1] Direct addressing Indirect addressing [1] In the direct addressing mode, HcTransferCounter must be set to 0001H. 9.6.1 Configuring registers for a DMA transfer To set up a DMA transfer, the following HC registers must be configured depending on the type of transfer required: * HcHardwareConfiguration - DREQ1 output polarity (bit 5) - DACK1 input polarity (bit 6) - DACK mode (bit 8). * HcPInterruptEnable - If you want an interrupt to be generated after the DMA transfer is complete, set EOTInterruptEnable (bit 3). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 26 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller * HcPInterrupt - Before initiating the DMA transfer, clear AllEOTInterrupt (bit 3). This bit is set when the DMA transfer is complete. * HcTransferCounter - If DMACounterEnable of the HcDMAConfiguration register is set (that is, the DMA counter is enabled), HcTransferCounter must be set to the number of bytes to be transferred. * HcDMAConfiguration - Read or write DMA (bit 0) - Targeted buffer: ISTL0, ISTL1, ATL and INTL (bits 1 to 3) - DMA enable or disable (bit 4) - Burst length (bits 5 to 6) - DMA counter enable (bit 7). Remark: Configure the HcDMAConfiguration register only after you have configured all the other registers. The ISP1362 will assert DREQ1 once the DMA enable bit in this register is set. 9.6.2 Combining the two DMA channels The ISP1362 allows systems with limited DMA channels to use a single DMA channel (DMA1) for both the HC and the DC. This option can be enabled by writing logic 1 to the OneDMA bit of the HcHardwareConfiguration register. If this option is enabled, the polarity of the DC DMA and the HC DMA must be set to DACK active LOW and DREQ active HIGH. 9.7 Interrupts Various events in the HC, the DC and the OTG controller can be programmed to generate a hardware interrupt. By default, the interrupt generated by the HC and the OTG controller is routed out at the INT1 pin and the interrupt generated by the DC is routed out at the INT2 pin. 9.7.1 Interrupt in the HC and the OTG controller There are two levels of interrupts represented by level 1 and level 2 (see Figure 14). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 27 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller OtgInterruptEnable register OTG_TMR_IE B_SE0_SRP_IE A_SRP_DET_IE OTG_RESUME_IE OTG_SUSPND_IE RMT_CONN_IE B_SESS_VLD_IE A_SESS_VLD_IE B_SESS_END_IE A_VBUS_VLD_IE ID_REG_IE OR OtgInterrupt register OTG_TMR_TIMEOUT B_SE0_SRP A_SRP_DET OTG_RESUME OTG_SUSPND RMT_CONN_C B_SESS_VLD_C A_SESS_VLD_C B_SESS_END_C A_VBUS_VLD_C ID_REG_C ISTL_0_InterruptEnable ISTL_1_InterruptEnable HCSuspendedEnable EOT_InterruptEnable OPRInterruptEnable SOFInterruptEnable AIIEOTInterrupt level 2 (OTG group) HcPInterrupt register HcPInterruptEnable register INTL_IRQ_InterruptEnable OTG_IRQ_InterruptEnable MIE RHSC FNO UE RD SF SO level 2 (OPR group) OR HcInterruptStatus register RHSC FNO UE RD SF SO INT1 LATCH LE From INT2 OneINT HcHardwareConfiguration register HcHardwareConfiguration register InterruptPinEnable 004aaa395 level 1 OR Fig 14. HC and OTG interrupt logic. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 ClkReady HcInterruptEnable register ATL_IRQ_InterruptEnable HcSuspended ISTL_0_INT ISTL_1_INT OPR_Reg INTL_IRQ OTG_IRQ ClkReady SOF_INT ATL_IRQ 28 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the HcInterruptStatus register). When any of these events occurs, the corresponding bit would be set to logic 1, and if the corresponding bit in the HcInterruptEnable register is also logic 1, the 6-input OR gate would output logic 1. This output is combined with the value of MIE (bit 31 of HcInterruptEnable) using the AND operation and logic 1 output at this AND gate will cause the OPR bit in the HcPInterrupt register to be set to logic 1. The interrupt level 2 (OTG group) contains 11 possible interrupt events (recorded in the OtgInterrupt register). When any of these events occurs, the corresponding bit would be set to logic 1, and if the corresponding bit in the OtgInterruptEnable register is also logic 1, the 11-input OR gate would output logic 1 and cause the OTG_IRQ bit in the HcPInterrupt register to be set to logic 1. The level 1 interrupts contains 10 possible interrupt events. The HcPInterrupt and HcPInterruptEnable registers work in the same way as the HcInterruptStatus and HcInterruptEnable registers. The output from the 10-input OR gate is connected to a latch, which is controlled by InterruptPinEnable (the bit 0 of HcHardwareConfiguration register). When the software wishes to temporarily disable the interrupt output of the ISP1362 HC and OTGC, follow this procedure: 1. Set the InterruptPinEnable bit in HcHardwareConfiguration register to logic 1. 2. Clear all bits in the HcPInterrupt register. 3. Set the InterruptPinEnable bit to logic 0. To re-enable the interrupt generation, set the InterruptPinEnable bit to logic 1. Remark: The InterruptPinEnable bit in the HcHardwareConfiguration register controls the latch of the interrupt output. When this bit is set to logic 0, the interrupt output will remain unchanged, regardless of any operation on the interrupt control registers. If INT1 is asserted, and the HCD wishes to temporarily mask off the INT signal without clearing the HcPInterrupt register, follow this procedure: 1. Make sure that the InterruptPinEnable bit is set to logic 1. 2. Clear all bits in the HcPInterruptEnable register. 3. Set the InterruptPinEnable bit to logic 0. To re-enable the interrupt generation: 1. Set all bits in the HcPInterruptEnable register according to the HCD requirements. 2. Set the InterruptPinEnable bit to logic 1. 9.7.2 Interrupt in the DC The registers that control the interrupt generation in the ISP1362 DC are: * DcMode (bit 3) * DcHardwareConfiguration (bits 0 and 1) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 29 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller * DcInterruptEnable * DcInterrupt. The DcMode register (bit 3) is the overall DC interrupt enable. DcHardwareConfiguration determines the following features: * Level-triggered or edge-triggered (bit 1) * Output polarity (bit 0). For details on the interrupt logic in the DC, refer to the Interrupt Control application note. 9.7.3 Combining INT1 and INT2 In some embedded systems, interrupt inputs to the CPU are a very scarce resource. The system designer might want to use just one interrupt line to serve the HC, the DC and the OTG controller. In such a case, make sure the OneINT feature is activated. When OneINT (bit 9 of the HcHardwareConfiguration register) is set to logic 1, both the INT1 (HC or OTG controller) interrupt and the INT2 (DC) interrupt are routed to pin INT1, thereby reducing hardware resource requirements. Remark: Both the host controller (or OTG controller) and the device controller interrupts must be set to the same polarity (active HIGH or active LOW) and the same trigger type (edge or level). Failure to conform to this will lead to unpredictable behavior of the ISP1362. 9.7.4 Behavior difference between level-triggered and edge-triggered interrupts In many microprocessor systems, the operating system disables an interrupt when it is in an Interrupt Service Routine (ISR). If there is an interrupt event during this period, it will lead to: Level-triggered interrupt: When the ISP1362 interrupt asserts, the operating system takes no action because it disables the interrupt when it is in the ISR. The interrupt line of the ISP1362 remains asserted. When the operating system exits the ISR and re-enables the interrupt processing, it sees the asserted interrupt line and immediately enters the ISR. Edge-triggered interrupt: When the ISP1362 outputs a pulse, the operating system takes no action because it disables the interrupt when it is in the ISR. The interrupt line of the ISP1362 goes back to the inactive state. When the operating system exits the ISR and re-enables the interrupt processing, it sees no pending interrupt. As a result, the interrupt is missed. If the system needs to know whether an interrupt (approximately 160 ns pulse width) occurs during this period, it may read the HcPInterrupt register (see Table 68). 10. Power-on reset (POR) When VCC is directly connected to the RESET pin, the internal POR pulse width (tPORP) will be typically 800 ns. The pulse is started when VCC rises above Vtrip (2.03 V). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 30 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller To give a better view of the functionality, Figure 15 shows a possible curve of VCC with dips at t2-t3 and t4-t5. If the dip at t4-t5 is too short (that is, < 11 s), the internal POR pulse will not react and will remain LOW. The internal POR starts with a HIGH at t0. At t1, the detector will see the passing of the trip level and a delay element will add another tPORP before it drops to LOW. The internal POR pulse will be generated whenever VCC drops below Vtrip for more than 11 s. V CC V trip t0 t1 t2 t3 t4 t5 PORP (1) t PORP t PORP 004aaa482 (1) PORP = power-on reset pulse. Fig 15. Internal power-on reset timing. The RESET pin can be either connected to VCC (using the internal POR circuit) or externally controlled (by the micro, ASIC, and so on). Figure 16 shows the availability of the clock with respect to the external reset pulse. RESET EXTERNAL CLOCK 004aaa484 A Stable external clock is available at A. Fig 16. Clock with respect to the external power-on reset. 11. On-The-Go (OTG) controller 11.1 Introduction OTG is a supplement to the Hi-Speed USB (USB 2.0) specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals. It is primarily targeted at portable devices because it addresses concerns related to such devices, such as a small connector and low power. Non-portable devices (even standard hosts), nevertheless, can also benefit from OTG features. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 31 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The ISP1362 OTG controller is designed to perform all the tasks specified in the OTG supplement. It supports Host Negotiation Protocol (HNP) and Session Request Protocol (SRP) for dual-role devices. The ISP1362 uses software implementation of HNP and SRP for maximum flexibility. A set of OTG registers provides the control and status monitoring capabilities to support software HNP or SRP. Besides the normal USB transceiver, timers and analog components required by OTG are also integrated on-chip. The analog components include: * * * * Built-in 3.3 V-to-5 V charge pump Voltage comparators Pull-up or pull-down resistors on data lines Charge or discharge resistors for VBUS. 11.2 Dual-role device When port 1 of the ISP1362 is configured in the OTG mode, it can be used as an OTG dual-role device. A dual-role device is a USB device that can function either as a host or as a peripheral. As a host, the ISP1362 can support all four types of transfers (control, bulk, isochronous and interrupt) at full-speed or low-speed. As a peripheral, the ISP1362 can support two control endpoints and up to 14 configurable endpoints, which can be programmed to any of the four transfer types. The default role of the ISP1362 is controlled by the ID pin, which in turn is controlled by the type of plug connected to the mini-AB receptacle. If ID = LOW (mini-A plug connected), it becomes an A-device, which is a host by default. If ID = HIGH (mini-B plug connected), it becomes a B-device, which is a peripheral by default. Both the A-device and the B-device work on a session base. A session is defined as the period of time in which devices exchange data. A session starts when VBUS is driven and ends when VBUS is turned off. Both the A-device and the B-device may start a session. During a session, the role of the host can be transferred back and forth between the A-device and the B-device any number of times by using HNP. If the A-device wants to start a session, it turns on VBUS by enabling the charge pump. The B-device detects that VBUS has risen above the B_SESS_VLD level and assumes the role of a peripheral asserting its pull-up resistor on the DP line. The A-device detects the remote pull-up resistor and assumes the role of a host. Then, the A-device can communicate with the B-device as long as it wishes. When the A-device finishes communicating with the B-device, the A-device turns-off VBUS and both the devices finally go into the idle state. See Figure 18 and Figure 19. If the B-device wants to start a session, it must initiate SRP by `data line pulsing' and `VBUS pulsing'. When the A-device detects any of these SRP events, it turns on its VBUS (note that only the A-device is allowed to drive VBUS). The B-device assumes the role of a peripheral, and the A-device assumes the role of a host. The A-device detects that the B-device can support HNP by getting the OTG descriptor from the B-device. The A-device will then enable the HNP hand-off by using SetFeature (b_hnp_enable) and then go into the `suspend' state. The B-device signals claiming the host role by deasserting its pull-up resistor. The A-device acknowledges by going into the peripheral state. The B-device then assumes the role of a host and 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 32 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller communicates with the A-device as long as it wishes. When the B-device finishes communicating with the A-device, both the devices finally go into the idle state. See Figure 18 and Figure 19. 11.3 Session Request Protocol (SRP) As a dual-role device, the ISP1362 can initiate and respond to SRP. The B-device initiates SRP by data line pulsing followed by VBUS pulsing. The A-device can detect either data line pulsing or VBUS pulsing. 11.3.1 B-device initiating SRP The ISP1362 can initiate SRP by performing the following steps: 1. Detect initial conditions [read ID_REG, B_SESS_END and SE0_2MS (bits 0, 2 and 9) of the OtgStatus register]. 2. Start data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 1]. 3. Wait for 5 ms to 10 ms. 4. Stop data line pulsing [set LOC_CONN (bit 4) of OtgControl register to logic 0]. 5. Start VBUS pulsing [set CHRG_VBUS (bit 1) of the OtgControl register to logic 1]. 6. Wait for 10 ms to 20 ms. 7. Stop VBUS pulsing [set CHRG_VBUS (bit 1) of the OtgControl register to logic 0]. 8. Discharge VBUS for about 30 ms [by using DISCHRG_VBUS (bit 2) of the OtgControl register], optional. The B-device must complete both data line pulsing and VBUS pulsing within 100 ms. 11.3.2 A-device responding to SRP The A-device must be able to respond to one of the two SRP events: data line pulsing or VBUS pulsing. The ISP1362 allows you to choose which SRP to support and has a mechanism to disable or enable the SRP detection. This is useful for some applications under certain cases. For example, if the A-device battery is low, it may not want to turn on its VBUS by detecting SRP. In this case, it may choose to disable the SRP detection function. When the data line SRP detection is used, the ISP1362 can detect either the DP pulsing or the DM pulsing. This means a peripheral-only device can initiate data line pulsing SRP through DP (full-speed) or DM (low-speed). A dual-role device will always initiate data line pulsing SRP through DP because it is a full-speed device. * Steps to enable the SRP detection by VBUS pulsing: - Set A_SEL_SRP (bit 9) of the OtgControl register to logic 0. - Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1. * Steps to enable the SRP detection by data line pulsing: - Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1. - Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1. * Steps to disable the SRP detection: - Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 0. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 33 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 11.4 Host Negotiation Protocol (HNP) HNP is used to transfer control of the host role between the default host (A-device) and the default peripheral (B-device) during a session. When the A-device is ready to give up its role as a host, it will condition the B-device by SetFeature (b_hnp_enable) and will go into `suspend'. If the B-device wants to use the bus at that time, it signals a `disconnect' to the A-device. Then, the A-device will take the role of a peripheral and the B-device will take the role of a host. 11.4.1 Sequence of HNP events The sequence of events for HNP as observed on the USB bus is illustrated in Figure 17. A-device 1 3 B-device 2 5 4 7 6 8 DP Composite 004aaa079 Legend DP driven Pull-up dominates Pull-down dominates Normal bus activity Fig 17. HNP sequence of events. As can be seen in Figure 17: 1. The A-device completes using the bus and stops all bus activity (that is, suspends the bus). 2. The B-device detects that the bus is idle for more than 5 ms and begins HNP by turning off the pull-up on DP. This allows the bus to discharge to the SE0 state. 3. The A-device detects SE0 on the bus and recognizes this as a request from the B-device to become a host. The A-device responds by turning on its DP pull-up within 3 ms of first detecting SE0 on the bus. 4. After waiting for 30 s to ensure that the DP line is not HIGH because of the residual effect of the B-device pull-up, the B-device notices that the DP line is HIGH and the DM line is LOW (that is, J state). This indicates that the A-device has recognized the HNP request from the B-device. At this point, the B-device becomes a host and asserts bus reset to start using the bus. The B-device must assert the bus reset (that is, SE0) within 1 ms of the time that the A-device turns on its pull-up. 5. When the B-device completes using the bus, it stops all bus activity. Optionally, the B-device may turn on its DP pull-up at this time. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 34 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 6. The A-device detects lack of bus activity for more than 3 ms and turns off its DP pull-up. Alternatively, if the A-device has no further need to communicate with the B-device, the A-device may turn off VBUS and end the session. 7. The B-device turns on its pull-up. 8. After waiting 30 s to ensure that the DP line is not HIGH because of the residual effect of the A-device pull-up, the A-device notices that the DP-line is HIGH (and the DM line is LOW) indicating that the B-device is signaling a connect and is ready to respond as a peripheral. At this point, the A-device becomes a host and asserts the bus reset to start using the bus. 11.4.2 OTG state diagrams Figure 18 and Figure 19 show the state diagrams for the dual-role A-device and the dual-role B-device, respectively. For a detailed explanation, refer to On-The-Go Supplement to the USB 2.0 Specification Rev. 1.0a. The OTG state machine is implemented with software. The inputs to the state machine come from four sources: hardware signals from the USB bus, software signals from the application program, internal variables with the state machines and timers: * Hardware inputs: Include id, a_vbus_vld, a_sess_vld, b_sess_vld, b_sess_end, a_conn, b_conn, a_bus_suspend, b_bus_suspend, a_bus_resume, b_bus_resume, a_srp_det and b_se0_srp. All these inputs can be derived from the OtgInterrupt and OtgStatus registers. * Software inputs: Include a_bus_req, a_bus_drop and b_bus_req. * Internal variables: Include a_set_b_hnp_en, b_hnp_enable and b_srp_done. * Timers: The HNP state machine uses four timers: a_wait_vrise_tmr, a_wait_bcon_tmr, a_aidl_bdis_tmr and b_ase0_brst, tmr. All timers are started on entry to and reset on exit from their associated states. The ISP1362 provides a programmable timer that can be used as any of these four timers. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 35 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller START a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ a_bus_drop/ & (a_bus_req | a_srp_det) id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof/ id | a_bus_drop id | a_bus_drop | a_wait_bcon_tmout a_wait_vrise drv_vbus loc_conn/ loc_sof/ b_bus_suspend id | a_bus_drop a_vbus_err drv_vbus/ loc_conn/ loc_sof/ a_vbus_vld/ a_vbus_vld/ id | a_bus_drop | a_vbus_vld | a_wait_vrise_tmout a_peripheral drv_vbus loc_conn loc_sof/ a_vbus_vld/ a_vbus_vld/ a_wait_bcon drv_vbus loc_conn/ loc_sof/ b_conn/ & a_set_b_hnp_en/ b_conn/ & a_set_b_hnp_en id | b_conn/ | a_bus_drop a_bus_req | b_bus_resume a_suspend drv_vbus loc_conn/ loc_sof/ a_bus_req/ | a_suspend_req a_host drv_vbus loc_conn/ loc_sof 004aaa077 id | a_bus_drop | a_aidl_bdis_tmout b_conn Fig 18. Dual-role A-device state diagram. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 36 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller START b_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ id/ a_idle drv_vbus/ chrg_vbus/ loc_conn/ loc_sof/ b_bus_req & b_sess_end & b_se0_srp id/ | b_sess_vld/ b_host chrg_vbus/ loc_conn/ loc_sof id/ | b_sess_vld/ id/ | b_sess_vld/ id/ | b_srp_done b_srp_init pulse loc_conn pulse chrg_vbus loc_sof/ b_sess_vld a_conn b_bus_req/ | a_conn/ a_bus_resume | b_ase0_brst_tmout b_wait_acon chrg_vbus/ loc_conn/ loc_sof/ b_bus_req & b_hnp_en & a_bus_suspend b_peripheral chrg_vbus/ loc_conn loc_sof/ 004aaa078 Fig 19. Dual-role B-device state diagram. 11.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality. It is implemented in the microprocessor system that is connected to the ISP1362. The ISP1362 provides all input status, the output control and timers to fully support the state machine transitions in Figure 18 and Figure 19. These registers include: * OtgControl register: provides control to VBUS driving, charging or discharging, data line pull-up or pull-down, SRP detection, and so on * OtgStatus register: provides status detection on VBUS and data lines including ID, VBUS session valid, session end, overcurrent, bus status * OtgInterrupt register: provides interrupts for status change in OtgStatus register bits and the OtgTimer time-out event * OtgInterruptEnable register: provides interrupt mask for OtgInterrupt register bits * OtgTimer register: provides 0.01 ms base programmable timer for use in the OTG state machine. The OTG interrupt is generated on the INT1 pin. It is shared with the HC interrupt. To enable the OTG interrupt, perform these steps: 1. Set the polarity and the level-triggering or edge-triggering mode of the HcHardwareConfiguration register (bits 1 and 2, default is level-triggered, active LOW). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 37 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 2. Set the corresponding bits of the OtgInterruptEnable register (bits 0 to 8, or some of them). 3. Set bit OTG_IRQ_InterruptEnable of the HcPInterruptEnable register (bit 9). 4. Set bit InterruptPinEnable of the HcHardwareConfiguration register (bit 0). When an interrupt is generated on INT1, perform these steps in the interrupt service routine to get the related OTG status: 1. Read the HcPInterrupt register. If OTG_IRQ (bit 9) is set, then step 2. 2. Read the OtgInterrupt register. If any of the bits 0 to 4 are set, then step 3. 3. Read the OtgStatus register. The OTG state machine routines are called when any of the inputs is changed. These inputs come from either OTG registers (hardware) or application program (software). The outputs of the state machine include control signals to the OTG register (for hardware) and states or error codes (for software). For more information, refer to the Philips document ISP136x Embedded Programming Guide. 11.5 Power saving in the idle state and during wake-up The ISP1362 can be put in the power saving mode if the OTG device is not in a session. This significantly reduces the power consumption. In this mode, both the DC and the HC are suspended. The PLL and the oscillator are stopped, and the charge pump is in the suspend state. As an OTG device, however, the ISP1362 is required to respond to the SRP event. To support this, a LazyClock is kept running when the chip is in the power saving mode. An SRP event will wake up the chip (that is, enable the PLL and the oscillator). Besides this, an ID change or B_SESS_VLD detection can also wake up the chip. These wake-up events can be enabled or disabled by programming the related bits of the OtgInterruptEnable register before putting the chip in the power saving mode. If the bit is set, then the corresponding event (status change) will wake up the ISP1362. If the bit is cleared, then the corresponding event will not wake up the ISP1362. You can also wake up the ISP1362 from the power saving mode by using software. This is accomplished by accessing any of ISP1362 registers. Accessing a register will assert CS of the ISP1362, and therefore, set it awake. 11.6 Current capacity of the OTG charge pump The ISP1362 uses a built-in charge pump to generate a 5 V VBUS supply from a 3.3 V 0.3 V voltage source. The only external component required is a capacitor. The value of this capacitor depends on the amount of current drive required. Table 7 provides two recommended capacitor values and the corresponding current drive. Table 7: 27 nF 82 nF Recommended capacitor values VCC 3.0 V to 3.6 V 3.0 V to 3.3 V 3.3 V to 3.6 V Current 8 mA 14 mA 20 mA Capacitance 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 38 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The connection of the external capacitor (Cext) is given in the partial schematics in Figure 20. Remark: If the internal charge pump is not used, Cext is not required. VBUS 0.1 F OTG VBUS 4.7 F ISP1362 CP_CAP2 Cext CP_CAP1 004aaa154 Fig 20. External capacitors connection. 12. USB Host Controller (HC) 12.1 USB states of the HC The USB HC in the ISP1362 has four USB states: USBOperational, USBReset, USBSuspend and USBResume. These states define the responsibilities of the HC related to the USB signaling and bus states. These signals are visible to the HC Driver (HCD), the software driver of the HC, by using the control registers of the ISP1362 USB HC. USBOperational USBReset write USBOperational write USBReset write USBOperational write USBResume USBReset USBSuspend write USBResume write or remote wake-up USBReset write USBSuspend MGT947 hardware or software reset Fig 21. USB HC states of the ISP1362. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 39 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The USB states are reflected in the HostControllerFunctionalState (HCFS) field of the HcControl register. The HCD is allowed to perform only the USB state transitions shown in Figure 21. 12.2 USB traffic generation USB traffic can be generated only when the ISP1362 USB HC is under the USBOperational state. Therefore, the HCD must set the ISP1362 USB HC into the USBOperational state. This is done by setting the HCFS field of the HcControl register before generating USB traffic. A brief flow of USB traffic generation is described as follows: 1. Reset the ISP1362 by using the RESET pin or the software reset. 2. Set the physical size of the ATL, interrupt, ISTL0 and ISTL1 buffers. 3. Write the 32-bit hexadecimal value 0x800000FD to the HcInterruptEnable register. This will enable all the interrupt events in the register to trigger the hardware interrupt (see Section 15.1.5). 4. Write the 16-bit hexadecimal value 0x002D to the HcHardwareConfiguration register. This will set up the HC to level triggered and active HIGH interrupt setting (see Section 15.4.1). 5. Write 0x05000B02 to HcRhDescriptorA and 0x00000000 to HcRhDescriptorB. 6. Write the 16-bit hexadecimal value 0x0680 to the HcControl register to set the ISP1362 into the Operation mode (see Section 15.1.2). 7. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. These registers contain the 32-bit hexadecimal value 0x00010100 (see Section 15.3.4). 8. Connect a full-speed device to one of the downstream ports or use a 1.5 k resistor to pull up the DP line (to emulate a full-speed device). 9. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. The hexadecimal value of one of the registers must change to 0x00010101 indicating that a device connection has been detected. 10. Write the 32-bit hexadecimal value 0x00000102 into either HcRhPortStatus[1] or HcRhPortStatus[2] depending on the port that is being used. 11. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. Depending on which port the USB device is connected to, one of the registers should contain the hexadecimal value 0x00010103. SOF packets should be visible on DP and DM now. The HcFmNumber register contains the current frame number, which is updated every milliseconds. Remark: The generation of SOF is completely performed by the ISP1362 hardware. In this state of operation, if a PTD is written to the buffer memory, it would be processed and sent. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 40 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 12.3 USB ports The ISP1362 has two USB ports: port 1 and port 2. Port 1 can be configured as a downstream port (host), an upstream port (device) or a dual-role port (OTG). Port 2 is a fixed downstream port. The function of port 1 depends on two input pins of the ISP1362, namely ID and OTGMODE. Table 8: L H H Port 1 function ID X L H Function of port 1 OTG host peripheral OTGMODE In the OTG mode, port 2 operates as an internal host. It is not advisable to expose the host port 2 to external devices because it will not respond to the SRP and HNP protocols. Besides, the current capability of VBUS may be different from the OTG port's. The USB compliance checklist states that one and only one USB mini-AB receptacle is allowed on an OTG device. 12.4 Philips Transfer Descriptor (PTD) The PTD provides a communication channel between the HCD and the ISP1362 USB HC. A PTD consists of a PTD header and a payload data. The size of the PTD header is 8 bytes, and it contains information required for data transfer, such as data packet size, transfer status and transfer token types. Payload data to be transferred within a particular frame must have a PTD as the header (see Figure 22). The ISP1362 has three types of PTDs: control and bulk transfer (aperiodic transfer) PTD, interrupt transfer PTD and isochronous (ISO) transfer PTD. In the control and bulk transfer PTD and the interrupt transfer PTD, the buffer area is separated into equal sized blocks that are determined by HcATLBlockSize and HcINTLBlockSize. For example, if the block size is defined as 32 bytes, the first PTD structure in the memory buffer will have an offset of 0 bytes and the second PTD structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the PTD header size (8 bytes)]. Because of the fixed block size of the ISP1362 HC, however, even a PTD with 4 bytes of payload will occupy all the 40 bytes in a block. In the isochronous PTD, the HC uses a more flexible method to calculate the PTD offset because each PTD can have a different payload size. The actual amount of space for the payload, however, must be a multiple of DWord. Therefore, a 10-byte payload must have a reserved data size of 12 bytes. Take for example there are four PTDs in the ISTL0 buffer area with payload sizes of 200 bytes, 10 bytes, 1023 bytes and 30 bytes. Then, the offset of each of these PTDs will be as follows: PTD1 (200 bytes) -- offset = 0 PTD2 (10 bytes) -- offset = (200 + 8) = 208 PTD3 (1023 bytes) -- offset = (200 + 8) + (12 + 8) = 228 PTD4 (30 bytes) -- offset = (200 + 8) + (12 + 8) + (1024 + 8) = 1260. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 41 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller PTD data stored in the HC buffer memory will not be processed unless the respective control bits (ATL_Active, INTL_Active, ISTL0_BufferFull or ISTL1_BufferFull) in HcBufferStatus are set. PTD data in the ATL or interrupt buffer memory can be disabled by setting the respective skip bit in HcATLSkipMap and HcINTLSkipMap. To skip a particular PTD in the ATL or interrupt buffer, the HCD may set the corresponding bit of the SkipMap register. For example, setting the HcATLSkipMap register to 0x0011 will cause the HC to skip the first and the fifth PTDs in the ATL buffer memory. Certain fields in the PTD header are used by the HC to inform the HCD about the status of the transfer. These fields are indicated by the `Status Update by HC' column. These fields are updated after every transaction to reflect the current status of the PTD. buffer memory top PTD header PTD data #1 payload data PTD header PTD data #2 payload data PTD header payload data PTD data #N bottom 004aaa121 Fig 22. PTD data stored in the buffer memory. Table 9: Bit Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7 [1] All reserved bits should be set to logic 0. Generic PTD structure: bit allocation 7 6 5 4 3 Active MaxPktSize[7:0] EndpointNumber[3:0] B5[7] reserved B5[6] reserved B7[7:0] B3[3] TotalBytes[7:0] DirToken[1:0] FunctionAddress[6:0] TotalBytes[9:8] Speed MaxPktSize[9:8] 2 Toggle 1 0 ActualBytes[7:0] CompletionCode[3:0] ActualBytes[9:8] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 42 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Special fields for ATL, interrupt and ISO[1] ATL reserved Ping-Pong Paired reserved Interrupt reserved reserved reserved PollingRate[7:5]; StartingFrame[4:0] ISTL (ISO) Last reserved reserved StartingFrame Table 10: Bit B3[3] B5[6] B5[7] B7[7:0] [1] All reserved bits should be set to logic 0. Table 11: Name Generic PTD structure: bit description Status update by HC Yes Yes Description This field contains the number of bytes that were transferred for this PTD. 0000 NoError General Transfer Descriptor (TD) or isochronous data packet processing completed with no detected errors. The last data packet from the endpoint contained a Cyclic Redundancy Check (CRC) error. The last data packet from the endpoint contained a bit stuffing violation. The last packet from the endpoint had data toggle Packet ID (PID) that did not match the expected value. TD was moved to the Done queue because the endpoint returned a STALL PID. The device did not respond to the token (IN) or did not provide a handshake (OUT). The check bits on PID from the endpoint failed on data PID (IN) or handshake (OUT). The received PID was not valid when encountered, or the PID value is not defined. The amount of data returned by the endpoint exceeded either the size of the maximum data packet allowed from the endpoint (found in the MaximumPacketSize field of ED) or the remaining buffer size. The endpoint returned is less than MaximumPacketSize and that amount was not sufficient to fill the specified buffer. reserved reserved During an IN, the HC received data from the endpoint faster than it could be written to the system memory. During an OUT, the HC could not retrieve data from the system memory fast enough to keep up with the USB data rate. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. ActualBytes[9:0] CompletionCode[3:0] 0001 CRC 0010 0011 BitStuffing DataToggleMismatch 0100 0101 0110 0111 1000 Stall DeviceNot Responding PIDCheckFailure UnexpectedPID DataOverrun 1001 DataUnderrun 1010 1011 1100 BufferOverrun 1101 BufferUnderrun 9397 750 12337 Product data Rev. 03 -- 06 January 2004 43 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 11: Name Active Generic PTD structure: bit description...continued Status update by HC Yes Description Set to logic 1 by firmware to enable the execution of transactions by the HC. When the transaction associated with this descriptor is completed, the HC sets this bit to logic 0 indicating that a transaction for this element should not be executed when it is next encountered in the schedule. This bit is used to generate or compare the data PID value (DATA0 or DATA1) for IN and OUT transactions. It is updated after each successful transmission or reception of a data packet. This indicates the maximum number of bytes that can be sent to or received from the endpoint in a single data packet. This is the USB address of the endpoint within the function. This indicates that it is the last PTD of a list. Logic 1 means that this PTD is the last PTD. The last PTD is used only for ISO. This bit is not used in interrupt and ATL transfers. The last PTD is indicated by the HcINTLLastPTD and HcATLLastPTD registers. This bit indicates the speed of the endpoint. 0 -- full-speed 1 -- low-speed Toggle Yes MaxPktSize[9:0] EndpointNumber[3:0] B3[3] Last (PTD) No No No Speed (low) No TotalBytes[9:0] B5[6] Ping-Pong B5[7] Paired No No No This specifies the total number of bytes to be transferred with this data structure. This can be greater than MaximumPacketSize. 0 -- This is the ping buffer of the paired buffer. Paired must be logic 1. 1 -- This is the pong buffer of the paired buffer. Paired must be logic 1. If this bit is set to logic 1, two PTDs of the same endpoint and address can be made active at the same time. This bit is used with the Ping-Pong bit. The first paired PTD always starts with Ping = 0. The pong PTD payload can be sent out only if the ping PTD payload is sent out. You can also monitor RAM_BUFFER _STATUS to see which PTD is currently active on the USB line. 00 -- set-up 01 -- OUT 10 -- IN 11 -- reserved DirToken[1:0] No FunctionAddress[6:0] B7[7:5] PollingRate B7[4:0] StartingFrame (interrupt only) B7[7:0] StartingFrame (ISO only) No No This field contains the USB address of the function containing the endpoint that this PTD refers to. These two fields together select a start frame number (5 bits) and polls the interrupt device at a rate specified by PollingRate (3 bits); see Section 12.6. The HC compares this byte with the current frame number (can be accessed from the HcFrameNumber register). The PTD will be processed and sent out only if the starting frame number equals to the current frame number. No 12.5 Features of the control and bulk transfer (aperiodic transfer) * A Paired PTD is a special feature that provides high performance single endpoint bulk transfer and handles set-up enumeration sequence within 1 ms. A paired PTD consists of two PTDs serving the same endpoint of a device that are set active and 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 44 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller placed in the ATL RAM at the same time. A paired PTD is designed specially for high performance of a single endpoint. They are identified by hardware by using the `Paired' bit in the PTD. * Possible to send up to a maximum of 18 USB bulk packets in 1 ms frame (1.152 Mbyte/s) by using the paired PTD feature. * Provides the status of every transfer endpoints (PTD) by monitoring the HcATLDoneMap of the ISP1362. This register provides information on which PTD transfers are complete. * Sets the IRQ after the user-specified number of transfers is done. * Skips any PTD that is wasting bandwidth by using HcATLSkipMap. 12.5.1 Sending a USB device request (Get Descriptor) This section provides an example on how a USB transfer descriptor `Get Descriptor' (commonly used in device enumeration) is used to illustrate the ISP1362 PTD application. To perform this example, make sure the ISP1362 is in the Operational state, and then connect a USB device (for example, a USB mouse) to a port. Remark: For details on the USB device request, refer to Chapter 9 of Universal Serial Bus Specification Rev. 2.0. Step 1: Set the HcATLBlockSize, HcATLSkip and HcATLLast registers to 0x0008, 0xFFFE and 0x0001, respectively. Step 2: A PTD is then constructed based on the information given in the following sample code. This sample code places information into the correct bit location within the 8 bytes of the PTD structure. ActualBytes (10 bits) = 0x00 CompletionCode (4 bits) = 0x0F Active (1 bit) = 1 Toggle (1 bit) = 0 MaxPacketSize (10 bits) = 8 EndpointNumber (4 bits) = 0 Speed (1 bit) = 0 (full-speed; use 1 for low-speed) DirToken (2 bits) = 0 (setup token) TotalBytes (10 bits) = 8 CompletedPTD 0xF800, 0x0008, 0x0008, 0x0000 Step 3: This array is then appended with an 8-byte payload that specifies the type of request the HC wants to send. For example, for Get Descriptor, the payload is 0x0680, 0x0100, 0x0000, 0x0012. Step 4: The 16 bytes of data is now a complete PTD with an accompanying payload. This array is then copied into the ATL buffer area. Table 12 shows the ATL buffer area. Table 12: Offset Data ATL buffer area 0 0xF800 1 0x0008 2 0x0008 3 0x0000 4 0x0680 5 0x0100 6 0x0000 7 0x0012 Step 5: After copying data into the ATL buffer, the HC must be notified that the ATL buffer is now full and ready to be processed. The ATL_Active bit of the HcBufferStatus register must be set to logic 1 to inform the HC that the data in the 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 45 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller ATL buffer is now ready for processing. Once the ATL_Active bit of the HcBufferStatus register is set, the USB packet is sent out. The active bit in the PTD is cleared once the PTD is sent. Depending on the outcome of the USB transfer, the 4-bit completion code is updated. 12.6 Features of the interrupt transfer * An interrupt transaction is sent out periodically, according to the `interrupt polling rate' as defined in the PTD. * An interrupt transaction causes an interrupt to the CPU only if the transaction is ACKed or has error conditions, such as STALL or no respond. An ACK condition occurs if data is received on the IN token or data is sent out on the OUT token. * An interrupt is activated only once every ms as long as there is ACK for different interrupt transactions in the interrupt transfer buffer. * Each interrupt transfer (PTD) placed in the INTL buffer can automatically hold or send data for more than 1 ms. This can be done using the parameters in the PTD. Table 13: 0 1 2 3 4 5 6 7 Interrupt polling StartingFrame N[4:0] Frame 0 to 31 Frame 0 to 31 Frame 0 to 31 Frame 0 to 31 Frame 0 to 31 Frame 0 to 31 Frame 0 to 31 Frame 0 to 31 Interrupt polling interval (2N) in ms 1 2 4 8 16 32 64 128 N bits [7:5] 12.7 Features of the isochronous (ISO) transfer * Supports multi-buffering by using the ISTL0 or ISTL1 toggling mechanism. * The CPU can decide (in ms) how fast it can serve the ISP1362. This gives the CPU the flexibility to decide how much time it takes to read and fill in the ISO data. * The ISTL buffer can be updated on-the-fly by using the direct addressing memory architecture. 12.8 Overcurrent protection circuit The ISP1362 has a built-in overcurrent protection circuitry. You can enable or disable this feature by setting or resetting AnalogOCEnable (bit 10) of the HcHardwareConfiguration register. If this feature is disabled, it is assumed that there is an external overcurrent protection circuitry. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 46 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 12.8.1 Using internal OC detection circuit An application using the internal OC detection circuit and internal 15 k pull-down resistors is shown in Figure 23, where DMn denotes either OTG_DM1 or H_DM2, while DPn denotes either OTG_DP1 or H_DP2. In this example, the HC Driver must set both AnalogOCEnable and ConnectPullDown_DS1 (bit 10 and bit 12 of the HcHardwareConfiguration register, respectively) to logic 1. When H_OCn detects an overcurrent status on a downstream port, H_PSWn will output HIGH to turn off the +5 V power supply to the downstream port VBUS. When there is no such detection, H_PSWn will output LOW to turn on the +5 V power supply to the downstream port VBUS. In general applications, you can use a P-channel MOSFET as the power switch for VBUS. Connect the +5 V power supply to the drain pole of the P-channel MOSFET, VBUS to the source pole, and H_PSWn to the gate pole. This voltage drop (V) across the drain and source poles can be called the overcurrent trip voltage. For the internal overcurrent detection circuit, a voltage comparator has been designed-in, with a nominal voltage threshold of 75 mV. Therefore, when the overcurrent trip voltage (V) exceeds the voltage threshold, H_PSWn will output a HIGH level to turn off the P-channel MOSFET. If the P-channel MOSFET has RDSon of 150 m, the overcurrent threshold will be 500 mA. The selection of a P-channel MOSFET with a different RDSon will result in a different overcurrent threshold. VDD_5V PSU_5V drain P_channel MOSFET FB2 C41(1) C17 0.1 F DGND gate source H_OCn C18 0.1 F R31 10 k H_PSWn VBUS DM DP GND chassis chassis 004aaa148 1 2 3 4 5 6 DGND DGND (1) 100 F for the host port or 4.7 F for the OTG port. Fig 23. Using internal OC detection circuit. 12.8.2 Using external OC detection circuit When VCC (pin 56) is connected to the +3.3 V power supply instead of the +5 V power supply, the internal OC detection circuit cannot be used. An external OC detection circuit must be used instead. Nevertheless, regardless of VCC connection, an external OC detection circuit can be used from time to time. To use an 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 47 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller external OC detection circuit, set AnalogOCEnable, bit 10 of register HcHardwareConfiguration, to logic 0. By default after reset this bit is set to logic 0. Therefore, the HC Driver does not need to clear this bit. Figure 24 shows how to use an external OC detection circuit. PSU_5V OC DETECTION VIN OC H_OCn FB2 C41(1) VOUT C17 0.1 F DGND EN H_PSWn VBUS DM DP GND chassis chassis 004aaa149 1 2 3 4 5 6 DGND DGND (1) 100 F for the host port or 4.7 F for the OTG port. Fig 24. Using external OC detection circuit. 12.8.3 OC detection circuit using internal charge pump in the OTG mode When port 1 is operating in the OTG mode, you may choose to use the internal charge pump to provide 5 V VBUS, or supply VBUS from an external source. In this mode, the overcurrent condition is detected by a drop in VBUS that will be sensed by the built-in comparator. The overcurrent condition causes a change in the A_VBUS_VLD bit of the OtgStatus register. The software has to clear the DRV_VBUS bit in the OtgControl register when it detects the A_VBUS_VLD bit turning to logic 0. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 48 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller H_OCn FB2 C41(1) C17 0.1 F DGND VBUS VBUS DM DP GND chassis chassis 004aaa150 1 2 3 4 5 6 DGND n.c. H_PSWn DGND (1) 100 F for the host port or 4.7 F for the OTG port. Fig 25. Using internal charge pump. 12.8.4 OC detection circuit using external 5 V power source in the OTG mode In the OTG mode using external 5 V power source for VBUS, the circuit and the operation are the same as that for the non-OTG mode (see Section 12.8.1 and Section 12.8.2). 12.9 ISP1362 HC Power Management In the ISP1362, the HC and the DC are suspended and waken up individually. The H_SUSPEND/H_WAKEUP and D_SUSPEND/D_WAKEUP pins must be pulled-up by a large resistor (100 k). In the suspend state, these pins are HIGH. To wake up the HC, these pins must be pulled LOW. The ISP1362 can be partially suspended (only the HC or only the DC). In the partially suspended state, clock circuit and PLL continue to work. To save power, both the HC and the DC must be set to the suspend mode. The HC can be suspended by writing 0x06C0 to the HcControl register. The HC can be set awake by one of the following ways: * LOW pulse on the H_SUSPEND/H_WAKEUP pin, minimum length of pulse is 25 ns. * LOW pulse on the chip select (CS) pin, minimum length of pulse is 25 ns. * Resume signal by USB devices connected to the downstream port. On waking up from the suspend state, the clock to the HC will sustain for 5 ms. Within this 5 ms, the HC Driver must set the HC to the operational mode by writing 0x0680 to the HcControl register. If the HcControl register remains in the suspend state (0x06C0) after waking up the HC, the HC will return to the suspend state after 5 ms. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 49 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 13. USB Device Controller (DC) The design of the DC in the ISP1362 is compatible with the Philips ISP1181B USB full-speed interface device IC. The functionality of the DC in the ISP1362 is similar to the ISP1181B in the 16-bit bus mode. In addition, the command and register sets are also the same. In general, the DC in the ISP1362 provides 16 endpoints for the USB device implementation. Each endpoint can be allocated RAM space in the on-chip ping pong buffer RAM. Remark: The ping pong buffer RAM for the DC is independent of the buffer RAM for the Host Controller (HC). When the buffer RAM is full, the DC transfers the data in the buffer RAM to the USB bus. When the buffer RAM is empty, an interrupt is generated to notify the microprocessor to feed in data. The transfer of data between a microprocessor and the DC can be done in either the Programmed I/O (PIO) mode or in the direct memory access (DMA) mode. 13.1 DC data transfer operation The following sessions explains how the DC in the ISP1362 handles an IN data transfer and an OUT data transfer. An IN data transfer means transfer from the ISP1362 to an external USB host (through the upstream port), and an OUT transfer means transfer from an external USB host to the ISP1362. In the device mode, the ISP1362 acts as a USB device. 13.1.1 IN data transfer * The arrival of the IN token is detected by the Serial Interface Engine (SIE) by decoding the Packet IDentifier (PID). * The SIE also checks the device number and the endpoint number to verify whether they are okay. * If the endpoint is enabled, the SIE checks the contents of the DcEndpointStatus register (ESR). If the endpoint is full, the contents of the buffer memory are sent during the data phase else an NAK handshake is sent. * After the data phase, the SIE expects a handshake (ACK) from the host (except for ISO endpoints). * On receiving the handshake (ACK), the SIE updates the contents of the DcEndpointStatus and DcInterrupt registers, which in turn generates an interrupt to the microprocessor. For ISO endpoints, the DcInterrupt register is updated as soon as data is sent because there is no handshake phase. * On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will know which endpoint has generated the interrupt and reads the contents of the corresponding ESR. If the buffer is empty, it fills up the buffer so that data can be sent by the SIE at the next IN token phase. 13.1.2 OUT data transfer * The arrival of the OUT token is detected by the SIE by decoding the PID. * The SIE checks the device and endpoint numbers to verify whether they are okay. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 50 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller * If the endpoint is enabled, the SIE checks the contents of the ESR. If the endpoint is empty, the data from USB is stored in the buffer memory during the data phase else a NAK handshake is sent. * After the data phase, the SIE sends a handshake (ACK) to the host (except for ISO endpoints). * The SIE updates the contents of the DcEndpointStatus register and the DcInterrupt register, which in turn generates an interrupt to the microprocessor. For ISO endpoints, the DcInterrupt register is updated as soon as data is received because there is no handshake phase. * On receiving an interrupt, the microprocessor reads the DcInterrupt register. It will know which endpoint has generated the interrupt and reads the content of the corresponding ESR. If the buffer is full, it empties the buffer so that data can be received by the SIE at the next OUT token phase. 13.2 Device DMA transfer 13.2.1 DMA for IN endpoint (internal DC to the external USB host) When the internal DMA handler is enabled and at least one buffer (ping or pong) is free, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus. As soon as it has access, it asserts the DACK2 line and starts writing data. The burst length is programmable. When the number of bytes equal to the burst length has been written, the DREQ2 line is deasserted. As a result, the DMA controller deasserts the DACK2 line and releases the bus. At that moment, the whole cycle restarts for the next burst. When the buffer is full, the DREQ2 line is deasserted and the buffer is validated (which means that it is sent to the host at the next IN token). When the DMA transfer is terminated, the buffer is also validated (even if it is not full). A DMA transfer is terminated when any of the following conditions are met: * The DMA count is complete * DMAEN = 0. Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1, the DC DMA controller handshake signals DREQ2 and DACK2 are routed to DREQ1 and DACK1. 13.2.2 DMA for OUT endpoint (external USB host to internal DC) When the internal DMA handler is enabled and at least one buffer is full, the DREQ2 line is asserted. The external DMA controller then starts negotiating for control of the bus, and as soon as it has access, it asserts the DACK2 line and starts reading data. The burst length is programmable. When the number of bytes equal to the burst length has been read, the DREQ2 line is deasserted. As a result, the DMA controller deasserts the DACK2 line and releases the bus. At that moment, the whole cycle restarts for the next burst. When all the data is read, the DREQ2 line is deasserted and the buffer is cleared (this means that it can be overwritten when a new packet arrives). A DMA transfer is terminated when any of the following conditions are met: * The DMA count is complete * DMAEN = 0. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 51 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Remark: If the OneDMA bit in the HcHardwareConfiguration register is set to logic 1, the DC DMA controller handshake signals DREQ2 and DACK2 are routed to DREQ1 and DACK1. When the DMA transfer is terminated, the buffer is also cleared (even if data is not completely read) and the DMA handler is automatically disabled. For the next DMA transfer, the DMA controller as well as the DMA handler must be re-enabled. 13.3 Endpoint description 13.3.1 Endpoints with programmable buffer memory size Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the USB host and the USB device. At design time, each endpoint is assigned a unique number (endpoint identifier, see Table 14). The combination of the device address (given by the host during enumeration), the endpoint number, and the transfer direction allows each endpoint to be uniquely referenced. The DC has 16 endpoints: endpoint 0 (control IN and OUT) and 14 configurable endpoints, which can be individually defined as interrupt, bulk or isochronous--IN or OUT. Each enabled endpoint has an associated buffer memory, which can be accessed either by using the programmed I/O interface mode or by using the DMA mode. 13.3.2 Endpoint access Table 14 lists the endpoint access modes and programmability. All endpoints support I/O mode access. Endpoints 1 to 14 also support the DMA mode access. DC buffer memory DMA access is selected and enabled using bits EPIDX[3:0] and DMAEN of the DcDMAConfiguration register. A detailed description of the DC DMA operation is given in Section 13.4. Table 14: Endpoint identifier 0 0 1 to 14 [1] [2] [3] Endpoint access and programmability Buffer memory size (bytes)[1] 64 (fixed) 64 (fixed) programmable Double buffering no no supported PIO mode access yes yes supported DMA mode access no no supported Endpoint type control OUT[2][3] control IN[2][3] programmable The total amount of the buffer memory storage allocated to enabled endpoints must not exceed 2462 bytes. IN: input for the USB host (DC transmits); OUT: output from the USB host (DC receives). The data flow direction is determined by the EPDIR bit of the DcEndpointConfiguration register. 13.3.3 Endpoint buffer memory size The size of the buffer memory determines the maximum packet size that the hardware can support for a given endpoint. Only enabled endpoints are allocated space in the shared buffer memory storage, disabled endpoints have zero bytes. Table 15 lists the programmable buffer memory sizes. The following bits of the DcEndpointConfiguration register (ECR) affect the buffer memory allocation: * Endpoint enable bit (FIFOEN) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 52 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller * Size bits of an enabled endpoint (FFOSZ[3:0]) * Isochronous bit of an enabled endpoint (FFOISO). Remark: A register change that affects the allocation of the shared buffer memory storage among endpoints must not be made while valid data is present in any buffer memory of the enabled endpoints. Such changes renders all buffer memory contents undefined. Table 15: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Programmable buffer memory size Non-isochronous 8 bytes 16 bytes 32 bytes 64 bytes reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved reserved Isochronous 16 bytes 32 bytes 48 bytes 64 bytes 96 bytes 128 bytes 160 bytes 192 bytes 256 bytes 320 bytes 384 bytes 512 bytes 640 bytes 768 bytes 896 bytes 1023 bytes FFOSZ[3:0] Each programmable buffer memory can be independently configured by using its ECR, but the total physical size of all enabled endpoints (IN plus OUT) must not exceed 2462 bytes. Table 16 shows an example of a configuration fitting in the maximum available space of 2462 bytes. The total number of logical bytes in the example is 1311. The physical storage capacity used for double buffering is managed by the device hardware and is transparent to the user. Table 16: Memory configuration example Logical size (bytes) 64 64 1023 16 16 64 64 Endpoint description control IN (64-byte fixed) control OUT (64-byte fixed) double-buffered 1023-byte isochronous endpoint 16-byte interrupt OUT 16-byte interrupt IN double-buffered 64-byte bulk OUT double-buffered 64-byte bulk IN Physical size (bytes) 64 64 2046 16 16 128 128 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 53 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 13.3.4 Endpoint initialization In response to the standard USB request Set Interface, the firmware must program all the 16 ECRs of the DC in sequence (see Table 14), whether endpoints are enabled or not. The hardware then automatically allocates buffer memory storage space. If all endpoints have been successfully configured, the firmware must return an empty packet to the control IN endpoint to acknowledge success to the host. If there are errors in the endpoint configuration, the firmware must stall the control IN endpoint. When reset by hardware or by the USB bus occurs, the DC disables all endpoints and clears all ECRs, except the control endpoint which is fixed and always enabled. An endpoint initialization can be done at any time. It is, however, valid only after enumeration. 13.3.5 Endpoint I/O mode access When an endpoint event occurs (a packet is transmitted or received), the associated endpoint interrupt bits (EPn) of the DcInterrupt register (IR) are set by the SIE. The firmware then responds to the interrupt and selects the endpoint for processing. The endpoint interrupt bit is cleared by reading the DcEndpointStatus register (ESR). The ESR also contains information on the status of the endpoint buffer. For an OUT (= receive) endpoint, the packet length and packet data can be read from the DC by using the Read Buffer command. When the whole packet has been read, the firmware sends a Clear Buffer command to enable the reception of new packets. For an IN (= transmit) endpoint, the packet length and data to be sent can be written to the DC by using the Write Buffer command. When the whole packet has been written to the buffer, the firmware sends a Validate Buffer command to enable data transmission to the host. 13.3.6 Special actions on control endpoints Control endpoints require special firmware actions. The arrival of a Set-up packet flushes the IN buffer and disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microprocessor needs to re-enable these commands by sending an Acknowledge Set-up command to both the control endpoints. This ensures that the last Set-up packet stays in the buffer and that no packets can be sent back to the host until the microprocessor has explicitly acknowledged that it has received the Set-up packet. 13.4 DC direct memory access (DMA) transfer DMA is a method to transfer data from one location to another in a computer system, without intervention of the CPU. Many different implementations of DMA exist. The DC supports the 8237 compatible mode. 8237 compatible mode: based on the DMA subsystem of the IBM personal computers (PC, AT and all its successors and clones); this architecture uses the Intel 8237 DMA controller and has separate address spaces for memory and I/O. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 54 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The following features are supported: * * * * 13.4.1 Single-cycle or burst transfers (up to 16 bytes per cycle) Programmable transfer direction (read or write) Multiple End-Of-Transfer (EOT) sources: internal conditions, short or empty packet Programmable signal levels on pins DREQ2 and DACK2. Selecting an endpoint for the DMA transfer The target endpoint for DMA access is selected using bits EPDIX[3:0] of the DcDMAConfiguration register, as shown in Table 17. The transfer direction (read or write) is automatically set by the EPDIR bit in the associated ECR, to match the selected endpoint type (OUT endpoint: read; IN endpoint: write). Asserting input DACK2 automatically selects the endpoint specified in the DcDMAConfiguration register, regardless of the current endpoint used for the I/O mode access. Table 17: Endpoint identifier 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Endpoint selection for DMA transfer EPIDX[3:0] 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Transfer direction EPDIR = 0 OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read OUT: read EPDIR = 1 IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write IN: write 13.4.2 8237 compatible mode The 8237 compatible DMA mode is selected by clearing the DAKOLY bit of the DcHardwareConfiguration register (see Table 114). The pin functions for this mode are shown in Table 18. Table 18: Symbol DREQ2 DACK2 EOT RD WR 8237 compatible mode: pin functions Description DMA request of DC DMA acknowledge of DC end of transfer read strobe write strobe I/O O I I I I Function DC requests a DMA transfer DMA controller confirms the transfer DMA controller terminates the transfer instructs the DC to put data on the bus instructs the DC to get data from the bus (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 Product data Rev. 03 -- 06 January 2004 55 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The DMA subsystem of an IBM-compatible PC is based on the Intel 8237 DMA controller. It operates as a `fly-by' DMA controller. Data is not stored in the DMA controller, but it is transferred between an I/O port and a memory address. A typical example of the DC in 8237 compatible DMA mode is given in Figure 26. The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA (Hold Acknowledge). The bus operation is controlled by MEMR (Memory Read), MEMW (Memory Write), IOR (I/O read) and IOW (I/O write). D0 to D15 RAM MEMR MEMW ISP1362 DREQ2 DACK2 RD WR DMA CONTROLLER 8237 DREQ DACK IOR IOW HRQ HLDA CPU HRQ HLDA 004aaa047 Fig 26. DC in 8327 compatible DMA mode. The following example shows the steps that occur in a typical DMA transfer: 1. The DC receives a data packet in one of its endpoint buffer memory. The packet must be transferred to memory address 1234H. 2. The DC asserts the DREQ2 signal requesting the 8237 for a DMA transfer. 3. The 8237 asks the CPU to release the bus by asserting the HRQ signal. 4. After completing the current instruction cycle, the CPU places the bus control signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and asserts HLDA to inform the 8237 that it has control of the bus. 5. The 8237 now sets its address lines to 1234H and activates the MEMW and IOR control signals. 6. The 8237 asserts DACK to inform the DC that it will start a DMA transfer. 7. The DC now places the word to be transferred on the data bus lines because its RD signal was asserted by the 8237. 8. The 8237 waits one DMA clock period and then deasserts MEMW and IOR. This latches and stores the word at the desired memory location. It also informs the DC that the data on the bus lines has been transferred. 9. The DC deasserts the DREQ2 signal to indicate to the 8237 that DMA is no longer needed. In the Single cycle mode, this is done after each byte or word; in the Burst mode, following the last transferred byte or word of the DMA cycle. 10. The 8237 deasserts the DACK output indicating that the DC must stop placing data on the bus. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 56 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 11. The 8237 places the bus control signals (MEMR, MEMW, IOR and IOW) and the address lines in three-state and deasserts the HRQ signal, informing the CPU that it has released the bus. 12. The CPU acknowledges control of the bus by deasserting HLDA. After activating the bus control lines (MEMR, MEMW, IOR and IOW) and the address lines, the CPU resumes the execution of instructions. For a typical bulk transfer, the preceding process is repeated 32 times, once for each word. After each word, the DcAddress register in the DMA controller is incremented by two and the byte counter is decremented by two. When using the 16-bit DMA, the number of transfers is 32 and address incrementing and byte counter decrementing is done by two for each word. 13.4.3 End-Of-Transfer conditions Bulk endpoints: A DMA transfer to or from a bulk endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConfiguration register, see Table 118 and Table 119): * The DMA transfer completes as programmed in the DcDMACounter register (CNTREN = 1) * A short packet is received on an enabled OUT endpoint (SHORTP = 1) * DMA operation is disabled by clearing the DMAEN bit. DcDMACounter register -- An EOT from the DcDMACounter register is enabled by setting bit CNTREN of the DcDMAConfiguration register. The DC has a 16-bit DcDMACounter register, which specifies the number of bytes to be transferred. When DMA is enabled (DMAEN = 1), the internal DMA counter is loaded with the value from the DcDMACounter register. When the internal counter completes the transfer as programmed in the DMA counter, an EOT condition is generated and the DMA operation stops. Short packet -- Normally, the transfer byte count must be set using a control endpoint before any DMA transfer takes place. When a short packet has been enabled as EOT indicator (SHORTP = 1), the transfer size is determined by the presence of a short packet in the data. This mechanism permits the use of a fully autonomous data transfer protocol. When reading from an OUT endpoint, reception of a short packet at an OUT token will stop the DMA operation after transferring the data bytes of this packet. Table 19: Summary of EOT conditions for a bulk endpoint OUT endpoint transfer completes as programmed in the DcDMACounter register short packet is received and transferred DMAEN = 0[1] IN endpoint transfer completes as programmed in the DcDMACounter register counter reaches zero in the middle of the buffer DMAEN = 0[1] EOT condition DcDMACounter register Short packet DMAEN bit of the DcDMAConfiguration register [1] The DMA transfer stops. No interrupt, however, is generated. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 57 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Isochronous endpoints: A DMA transfer to or from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConfiguration register, see Table 118 and Table 119): * The DMA transfer completes as programmed in the DcDMACounter register (CNTREN = 1) * An End-Of-Packet (EOP) signal is detected * DMA operation is disabled by clearing bit DMAEN. Table 20: Recommended EOT usage for isochronous endpoints OUT endpoint do not use IN endpoint preferred EOT condition DcDMACounter register zero 13.5 ISP1362 DC suspend and resume 13.5.1 Suspend conditions The DC in the ISP1362 detects a USB suspend condition in either of the following cases: * Constant idle state is present on the USB bus for 3 ms. * VBUS is lost. Bus-powered devices that are suspended must not consume more than 500 A of current. This is achieved by shutting down the power to system components or supplying them with a reduced voltage. The steps leading the DC to the suspend state are as follows: 1. In the event of no SOF for 3 ms, the DC in the ISP1362 sets bit SUSPND of the DcInterrupt register. This will generate an interrupt if bit IESUSP of the DcInterruptEnable register is set. 2. When the firmware detects a suspend condition (through the IESUSP), it must prepare all system components for the suspend state: a. All the signals connected to the DC in the ISP1362 must enter appropriate states to meet the power consumption requirements of the suspend state. b. All the input pins of the DC in the ISP1362 must have a CMOS logic 0 or logic 1 level. 3. In the interrupt service routine, the firmware must check the current status of the USB bus. When bit BUSTATUS of the DcInterrupt register is logic 0, the USB bus has left the suspend mode and the process must be aborted. Otherwise, the next step can be executed. 4. To meet the suspend current requirements for a bus-powered device, the internal clocks must be switched off by clearing bit CLKRUN of the DcHardwareConfiguration register. 5. When the firmware has set and cleared the GOSUSP bit of the DcMode register, the DC in the ISP1362 enters the suspend state. It sets the D_SUSPEND/D_WAKEUP pin to HIGH and switches off the internal clocks after 2 ms. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 58 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The DC in the ISP1362 will remain in the suspend state for at least 5 ms, before responding to external wake-up events, such as global resume, bus traffic, CS active or LOW pulse on the D_SUSPEND/D_WAKEUP pin. Figure 27 shows a typical timing diagram for the DC suspend and resume operations. A > 5 ms idle state USB BUS > 3 ms INT2 suspend interrupt B GOSUSP (bit) resume interrupt D 10 ms K-state D_SUSPEND/D_WAKEUP 1.8 ms to 2.2 ms 0.5 ms to 3.5 ms CS C 004aaa483 Fig 27. Suspend and resume timing. In Figure 27: A -- indicates the point at which the USB bus goes to the idle state. B -- after detecting the suspend interrupt, set and clear the GOSUSP bit in the Mode register. C -- indicates resume condition, which can be a resume signal from the host, a LOW pulse on the D_SUSPEND/D_WAKEUP pin, or a LOW pulse on the CS pin. D -- indicates remote wake-up. The ISP1362 will drive a K-state on the USB bus for 10 ms after the D_SUSPEND/D_WAKEUP pin goes LOW or the CS pin goes LOW. 13.5.2 Resume conditions Wake-up from the suspend state is initiated either by the USB host or by the application: * USB host: drives a K-state on the USB bus (global resume) * Application: remote wake-up using a LOW pulse on pin D_SUSPEND/D_WAKEUP or a LOW pulse on pin CS (if enabled using bit WKUPCS of the DcHardwareConfiguration register). The steps of a wake-up sequence are as follows: 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 59 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, the clock signals are routed to all internal circuits of the DC in the ISP1362. 2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of the DcInterrupt register is set. This will generate an interrupt if bit IERESUME of the DcInterruptEnable register is set. 3. 5 ms after starting the wake-up sequence, the DC in the ISP1362 resumes its normal functionality (this could be set to 100 s by setting pin TEST0 to HIGH). 4. In case of a remote wake-up, the DC in the ISP1362 drives a K-state on the USB bus for 10 ms. 5. The application restores itself and other system components to normal operating mode. 6. After wake-up, the internal registers of the DC in the ISP1362 are read and write-protected to prevent corruption by inadvertent writing during power-up of external components. The firmware must send an Unlock Device command to the DC in the ISP1362 to restore its full functionality. 14. OTG registers Table 21: Read 62 67 68 69 6A 6C OTG Control registers summary Register OtgControl OtgStatus OtgInterrupt OtgInterruptEnable OtgTimer OtgAltTimer Width 16 16 16 16 32 32 References Section 14.1 on page 60 Section 14.2 on page 62 Section 14.3 on page 63 Section 14.4 on page 66 Section 14.5 on page 67 Section 14.6 on page 68 Functionality OTG Operation registers Write E2 N/A E8 E9 EA EC Command (Hex) 14.1 OtgControl register (R/W: 62H/E2H) Code (Hex): 62 -- read Code (Hex): E2 -- write Table 22: Bit Symbol Reset Access Bit Symbol 7 LOC_ PULLDN_ DM 1 R/W 6 LOC_ PULLDN_ DP 1 R/W OtgControl register: bit allocation 15 14 reserved 5 A_RDIS_ LCON_EN 0 R/W 4 LOC_ CONN 0 R/W 13 12 11 OTG_SE0_ EN 0 R/W 3 SEL_CP_ EXT 0 R/W 10 A_SRP_ DET_EN 0 R/W 2 DISCHRG_ VBUS 0 R/W 9 A_SEL_ SRP 0 R/W 1 CHRG_ VBUS 0 R/W 8 SEL_HC_ DC 1 R/W 0 DRV_ VBUS 0 R/W Reset Access 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 60 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller OtgControl register: bit description Symbol Description reserved Table 23: Bit 11 15 to 12 - OTG_SE0_ This bit is used by the HC to send SE0 on remote connect. EN 0 -- No SE0 sent on remote connect detection 1 -- SE0 (bus reset) sent on remote connect detection Remark: This bit is normally set when the B-device goes into the b_wait_acon state (recommended sequence: LOC_CONN = 0 -> DELAY -> 50 s -> OTG_SE0_EN = 1 -> SEL_HC_DC = 0) and is cleared when it comes out of the b_wait_acon state. 10 A_SRP_ DET_EN This bit is for the A-device only. If set, the A_SRP_DET bit in the OtgInterrupt register will be set on detecting an SRP event. 0 -- disable 1 -- enable 9 A_SEL_ SRP This bit is for the A-device to select a method for detecting the SRP event (VBUS pulsing or data line pulsing). 0 -- A-device responds to VBUS pulsing 1 -- A-device responds to data line pulsing 8 SEL_HC_ DC This bit is used to select either the DC or the HC that interfaces with the transceiver. 0 -- HC SIE is connected to the OTG transceiver 1 -- DC SIE is connected to the OTG transceiver 7 LOC_ PULLDN_ DM LOC_ PULLDN_ DP A_RDIS_ LCON_EN 0 -- disconnects the on-chip pull-down resistor on DM of the OTG port 1 -- connects the on-chip pull-down resistor on DM of the OTG port 0 -- disconnects the on-chip pull-down resistor on DP of the OTG port 1 -- connects the on-chip pull-down resistor on DP of the OTG port This bit is for the A-device only. If set, the chip will automatically enable its pull-up resistor on DP upon detecting a remote disconnect event. If cleared, the DP pull-up is controlled by the LOC_CONN bit. 0 -- disable 1 -- enable Remark: This bit is normally set when the A-device goes into the a_suspend state and is cleared when it comes out of the a_suspend state. The LOC_CONN bit must be set before clearing this bit. 6 5 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 61 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller OtgControl register: bit description...continued Symbol LOC_ CONN SEL_CP_ EXT Description 0 -- disconnect the on-chip pull-up resistor on DP of the OTG port 1 -- connect the on-chip pull-up resistor on DP of the OTG port This bit is for the A-device only. This bit is used to choose the power source to drive VBUS. 0 -- use on-chip charge pump to drive VBUS 1 -- use external power source (+5 V) to drive VBUS Remark: When using the external power source, the H_PSW1 pin serves as the power switch that is controlled by the DRV_VBUS bit of this register. Table 23: Bit 4 3 2 DISCHRG_ This bit is for the B-device only. If set, it will enable a pull-down VBUS resistor on VBUS, which will help to speed up discharging of VBUS below session end threshold voltage. 0 -- disable 1 -- enable 1 CHRG_ VBUS This bit is for the B-device only. If set, it will charge VBUS through a resistor. 0 -- disable charging VBUS of the OTG port 1 -- enable charging VBUS of the OTG port 0 DRV_VBUS This bit is used to enable the on-chip charge pump or external power source to drive VBUS. For the B-device, it shall not enable this bit at any time. 0 -- disable driving VBUS of the OTG port 1 -- enable driving VBUS of the OTG port 14.2 OtgStatus register (R: 67H) Code (Hex): 67 -- read only Table 24: Bit Symbol Reset Access Bit Symbol Reset Access 7 reserved 6 5 RMT_ CONN 0 R OtgStatus register: bit allocation 15 14 13 reserved 4 B_SESS_ VLD 0 R 3 A_SESS_ VLD 0 R 2 B_SESS_ END 1 R 12 11 10 9 SE0_2MS 0 R 1 A_VBUS_ VLD 0 R 8 reserved 0 ID_REG 1 R 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 62 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller OtgStatus register: bit description Symbol SE0_2MS Description reserved 0 -- bus is in SE0 for less than 2 ms 1 -- bus is in SE0 for more than 2 ms Table 25: Bit 15 to 10 9 8 to 6 5 RMT_ CONN reserved 0 -- remote pull-up resistor disconnected 1 -- remote pull-up resistor connected Remark: When the local pull-up resistor on the DP-line is disabled, a 50 s delay is applied before RMT_CONN detection is enabled. 4 B_SESS_VLD For the B-device (ID_REG = 1), this bit is a B-device session valid indicator (B_SESS_VLD). 0 -- VBUS is lower than VB_SESS_VLD 1 -- VBUS is higher than VB_SESS_VLD 3 A_SESS_VLD For the A-device (ID_REG = 0), this bit is an A-device session valid indicator (A_SESS_VLD). 0 -- VBUS is lower than VA_SESS_VLD 1 -- VBUS is higher than VA_SESS_VLD 2 B_SESS_END For the B-device (ID_REG = 1), this bit is a B-device session end indicator (B_SESS_END). 0 -- VBUS is higher than VB_SESS_END 1 -- VBUS is lower than VB_SESS_END 1 A_VBUS_VLD For the A-device (ID_REG = 0), this bit is an A-device VBUS valid indicator (A_VBUS_VLD). 0 -- VBUS is lower than VA_VBUS_VLD 1 -- VBUS is higher than VA_VBUS_VLD 0 ID_REG This bit reflects the logic level of the ID pin. 0 -- ID pin is LOW (mini-A plug is inserted in the device's mini-AB receptacle) 1 -- ID pin is HIGH (no plug or mini-B plug is inserted in the device's mini-AB receptacle) 14.3 OtgInterrupt register (R/W: 68H/E8H) Code (Hex): 68 -- read Code (Hex): E8 -- write 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 63 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 26: Bit Symbol Reset Access Bit Symbol Reset Access OtgInterrupt register: bit allocation 15 14 13 reserved 7 OTG_ RESUME 0 R/W 6 OTG_ SUSPND 0 R/W Table 27: Bit 15 to 11 10 5 RMT_ CONN_C 0 R/W 4 B_SESS_ VLD_C 0 R/W 3 A_SESS_ VLD_C 0 R/W 12 11 10 OTG_TMR _TIMEOUT 0 R/W 2 B_SESS_ END_C 0 R/W 9 B_SE0_ SRP 0 R/W 1 A_VBUS_ VLD_C 0 R/W 8 A_SRP_ DET 0 R/W 0 ID_REG_C 0 R/W OtgInterrupt register: bit description Symbol Description reserved OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing TIMEOUT logic 1 clears this bit. Writing logic 0 has no effect. 0 -- no event 1 -- OTG Timer time-out 9 B_SE0_ SRP This bit is set whenever the device detects more than 2 ms of SE0. Writing logic 1 clears this bit. Writing logic 0 has no effect. 0 -- no event 1 -- bus has been in SE0 for more than 2 ms 8 A_SRP_ DET This bit is used to detect the session request event (SRP) from the remote device. The SRP event can be either VBUS pulsing or data line pulsing. Bit 9 (A_SEL_SRP) of the OtgControl register determines which SRP is selected. Writing logic 1 clears this bit. Writing logic 0 has no effect. 0 -- no event 1 -- SRP is detected 7 OTG_ RESUME This bit is used to detect a J to K state change when the device is in the `suspend' state. Writing logic 1 clears this bit. Writing logic 0 has no effect. 0 -- no event 1 -- a resume signal (J K) is detected when the bus is in the `suspend' state 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 64 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller OtgInterrupt register: bit description...continued Symbol OTG_ SUSPND Description This bit is set whenever the OTG port goes into the suspend state (bus idle for > 3 ms). Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- suspend (bus idle for > 3 ms) Table 27: Bit 6 5 RMT_ CONN_C This bit is set whenever the RMT_CONN bit of the OtgStatus register changes. Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- RMT_CONN bit has changed 4 B_SESS_ VLD_C This bit is set whenever the B_SESS_VLD bit of the OtgStatus register changes. Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- bit B_SESS_VLD has changed 3 A_SESS_ VLD_C This bit is set whenever the A_SESS_VLD bit of the OtgStatus register changes. Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- bit A_SESS_VLD has changed 2 B_SESS_ END_C This bit is set whenever the B_SESS_END bit of the OtgStatus register changes. Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- bit B_SESS_END has changed 1 A_VBUS_ VLD_C This bit is set whenever the A_VBUS_VLD bit of the OtgStatus register changes. Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- bit A_VBUS_VLD has changed 0 ID_REG_C This bit is set whenever the ID_REG bit of the OtgStatus register changes. This is an indication that the mini-A plug is inserted or removed (that is, the ID pin is shorted to ground or pulled HIGH). Write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no event 1 -- ID_REG bit has changed 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 65 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 14.4 OtgInterruptEnable register (R/W: 69H/E9H) Code (Hex): 69 -- read Code (Hex): E9 -- write Table 28: Bit Symbol Reset Access Bit Symbol 7 OTG_ RESUME_ IE 0 R/W 6 OTG_ SUSPND_ IE 0 R/W Table 29: Bit 15 to 11 10 9 8 7 OtgInterruptEnable register: bit allocation 15 14 13 reserved 5 RMT_ CONN_IE 0 R/W 4 B_SESS_ VLD_IE 0 R/W 3 A_SESS_ VLD_IE 0 R/W 12 11 10 OTG_ TMR_IE 0 R/W 2 B_SESS_ END_IE 0 R/W 9 B_SE0_ SRP_IE 0 R/W 1 A_VBUS_ VLD_IE 0 R/W 8 A_SRP_ DET_IE 0 R/W 0 ID_REG_ IE 0 R/W Reset Access OtgInterruptEnable register: bit description Symbol OTG_ TMR_IE B_SE0_ SRP_IE A_SRP_ DET_IE OTG_ RESUME_ IE OTG_ SUSPND_ IE RMT_ CONN_IE B_SESS_ VLD_IE A_SESS_ VLD_IE B_SESS_ END_IE A_VBUS_ VLD_IE Description reserved Logic 1 enables interrupt when the OTG timer attains time-out. Logic 1 enables interrupt upon detection of the B_SE0_SRP status change. Logic 1 enables interrupt upon detection of the SRP event. Logic 1 enables interrupt upon detection of bus resume (J to K only) event. Logic 1 enables interrupt upon detection of the bus `suspend' status change. Logic 1 enables interrupt upon detection of the RMT_CONN status change. Logic 1 enables interrupt upon detection of B_SESS_VLD status change. Logic 1 enables interrupt upon detection of A_SESS_VLD status change. Logic 1 enables interrupt upon detection of B_SESS_END status change. Logic 1 enables interrupt upon detection of A_VBUS_VLD status change. 6 5 4 3 2 1 0 ID_REG_IE Logic 1 enables interrupt upon detection of the ID_REG status change. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 66 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 14.5 OtgTimer register (R/W: 6AH/EAH) Code (Hex): 6A -- read Code (Hex): EA -- write Table 30: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W Table 31: Bit 31 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 0 R/W 15 0 R/W 14 0 R/W 13 OtgTimer register: bit allocation 31 START_ TMR 0 R/W 23 22 21 20 0 R/W 12 0 R/W 4 0 R/W 30 29 28 27 reserved 19 0 R/W 11 0 R/W 3 0 R/W 18 0 R/W 10 0 R/W 2 0 R/W 17 0 R/W 9 0 R/W 1 0 R/W 16 0 R/W 8 0 R/W 0 0 R/W 26 25 24 TMR_INIT_VALUE[23:16] TMR_INIT_VALUE[15:8] TMR_INIT_VALUE[7:0] OtgTimer register: bit description Symbol START_ TMR Description This is the start or stop bit of the OTG timer. Writing logic 1 will cause the OTG timer to load TMR_INIT_VALUE into the counter and start to count. Writing logic 0 will stop the timer. This bit is automatically cleared when the OTG timer is timed out. 0 -- stop the timer 1 -- start the timer 30 to 24 23 to 0 - reserved TMR_INIT_ These bits define the initial value used by the OTG timer. The timer VALUE interval is 0.01 ms. Maximum timer allowed is 167.772 s. [23:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 67 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 14.6 OtgAltTimer register (R/W: 6CH/ECH) Code (Hex): 6C -- read Code (Hex): EC -- write Table 32: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R Table 33: Bit 31 0 R 0 R 7 0 R 6 0 R 5 0 R 15 0 R 14 0 R 13 OtgAltTimer register: bit allocation 31 START_ TMR 0 R/W 23 22 21 20 0 R 12 0 R 4 0 R 30 29 28 27 reserved 19 0 R 11 0 R 3 0 R 18 0 R 10 0 R 2 0 R 17 0 R 9 0 R 1 0 R 16 0 R 8 0 R 0 0 R 26 25 24 CURRENT_TIME[23:16] CURRENT_TIME[15:8] CURRENT_TIME[7:0] OtgAltTimer register: bit description Symbol START_ TMR Description This is the start or stop bit of the OTG timer 2. Writing logic 1 will cause the OTG timer 2 to start counting from 0. When the counter reaches FFFFFFH, this bit is auto-cleared (the counter is stopped). Writing logic 0 will stop the counting. If any bit of the OTGInterrupt register is set and the corresponding bit of the OtgInterruptEnable register is also set, this bit will be auto-cleared and the current value of the counter will be written to the CURRENT_TIME field. 0 -- stop the timer 1 -- start the timer 30 to 24 23 to 0 - reserved CURRENT_ When read, these bits give the current value of the timer. The TIME actual time is CURRENT_TIME x 0.01 ms. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 68 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15. HC registers The HC contains a set of on-chip control registers. These registers can be read or written by the HC Driver (HCD). The Control and Status register set, the Frame Counter register set and the Root Hub register set are grouped under the category of HC operational registers (32 bits). These operational registers are made compatible to Open Host Controller Interface (OpenHCI) operational registers. This enables the OpenHCI HCD to be ported easily to the ISP1362. Reserved bits may be defined in future releases of this specification. To ensure interoperability, the HCD that does not use a reserved field must not assume that the reserved field contains logic 0. Furthermore, the HCD must always preserve the values of the reserved field. When a R/W register is modified, the HCD must first read the register, modify the desired bits and then write the register with the reserved bits still containing the read value. Alternatively, the HCD can maintain an in-memory copy of previously written values that can be modified and then written to the HC register. When there is a write to set or clear the register, bits written to reserved fields must be logic 0. As shown in Table 34, the offset locations (the commands for reading registers) of these operational registers (32-bit registers) are similar to those defined in the OHCI specification. The addresses, however, are equal to offset divided by 4. Table 34: Read 00 01 02 03 04 05 0D 0E 0F 11 12 13 14 15 16 20 21 22 24 25 HC Control registers summary Register HcRevision HcControl HcCommandStatus HcInterruptStatus HcInterruptEnable HcInterruptDisable HcFmInterval HcFmRemaining HcFmNumber HcLSThreshold HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1] HcRhPortStatus[2] HcHardwareConfiguration HcDMAConfiguration HcTransferCounter HcPInterrupt HcPInterruptEnable Width 32 32 32 32 32 32 32 32 32 32 32 32 32 32 32 16 16 16 16 16 Reference Section 15.1.1 on page 71 Section 15.1.2 on page 71 Section 15.1.3 on page 73 Section 15.1.4 on page 74 Section 15.1.5 on page 75 Section 15.1.6 on page 76 Section 15.2.1 on page 78 Section 15.2.2 on page 79 Section 15.2.3 on page 80 Section 15.2.4 on page 81 Section 15.3.1 on page 82 Section 15.3.2 on page 84 Section 15.3.3 on page 85 Section 15.3.4 on page 87 Section 15.3.4 on page 87 Section 15.4.1 on page 92 Section 15.4.2 on page 94 Section 15.4.3 on page 95 Section 15.4.4 on page 95 Section 15.4.5 on page 97 HC DMA and Interrupt Control registers HC Root Hub registers HC Frame Counter registers Functionality HC Control and Status registers Write N/A 81 82 83 84 85 8D 8E 8F 91 92 93 94 95 96 A0 A1 A2 A4 A5 Command (Hex) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 69 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 34: Read 27 28 N/A 2C 32 45 30 40 42 47 33 43 53 17 18 19 1A 34 44 54 1B 1C 1D 1E 51 52 HC Control registers summary...continued Register HcChipID HcScratch HcSoftwareReset HcBufferStatus HcDirectAddressLength HcDirectAddressData HcISTLBufferSize HcISTL0BufferPort HcISTL1BufferPort HcISTLToggleRate HcINTLBufferSize HcINTLBufferPort HcINTLBlkSize HcINTLPTDDoneMap HcINTLPTDSkipMap HcINTLLastPTD HcINTLCurrentActivePTD HcATLBufferSize HcATLBufferPort HcATLBlkSize HcATLPTDDoneMap HcATLPTDSkipMap HcATLLastPTD HcATLCurrentActivePTD HcATLPTDDoneThresholdCount Width 16 16 16 16 32 16 16 16 16 16 16 16 16 32 32 32 16 16 16 16 32 32 32 16 16 Reference Section 15.5.1 on page 98 Section 15.5.2 on page 98 Section 15.5.3 on page 99 HC Buffer RAM Section 15.6.2 on page 100 Control registers Section 15.6.3 on page 101 Section 15.7.1 on page 101 ISO Transfer registers Section 15.7.2 on page 101 Section 15.7.3 on page 102 Section 15.7.4 on page 102 Section 15.8.1 on page 103 Interrupt Transfer Section 15.8.2 on page 103 registers Section 15.8.3 on page 104 Section 15.8.4 on page 104 Section 15.8.5 on page 105 Section 15.8.6 on page 105 Section 15.8.7 on page 105 Section 15.9.1 on page 106 Aperiodic Transfer Section 15.9.2 on page 106 registers Section 15.9.3 on page 107 Section 15.9.4 on page 107 Section 15.9.5 on page 108 Section 15.9.6 on page 108 Section 15.9.7 on page 108 Section 15.9.8 on page 109 Section 15.9.9 on page 109 Section 15.6.1 on page 99 Functionality HC Miscellaneous registers Write N/A A8 A9 AC B2 C5 B0 C0 C2 C7 B3 C3 D3 N/A 98 99 N/A B4 C4 D4 N/A 9C 9D N/A D1 D2 Command (Hex) HcATLPTDDoneThresholdTimeOut 16 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 70 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.1 HC control and status registers 15.1.1 HcRevision register (R: 00H) The bit allocation of the HcRevision register is given in Table 35. Code (Hex): 00 -- read only Table 35: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R Table 36: Bit 31 to 8 7 to 0 0 R 1 R 7 6 5 4 REV[7:0] 0 R 0 R 0 R 1 R 15 14 13 12 reserved 3 2 1 0 23 22 21 20 reserved 11 10 9 8 HcRevision register: bit allocation 31 30 29 28 reserved 19 18 17 16 27 26 25 24 HcRevision register: bit description Symbol - REV[7:0] Description Reserved Revision: This read-only field contains the Binary-Coded Decimal (BCD) representation of the version of the HCI specification that is implemented by this HC. For example, a value of 11H corresponds to version 1.1. All HC implementations that are compliant with this specification need to have a value of 11H. 15.1.2 HcControl register (R/W: 01H/81H) The HcControl register defines the operating modes for the HC. The RWE bit is modified only by the HCD. Table 37 shows the bit allocation of the register. Code (Hex): 01 -- read Code (Hex): 81 -- write Table 37: Bit Symbol Reset Access HcControl register: bit allocation 31 30 29 28 reserved 27 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 71 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 21 13 reserved 5 20 reserved 12 4 19 11 3 reserved 18 10 RWE 0 R/W 2 17 9 RWC 0 R/W 1 16 8 reserved 0 - Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 23 15 7 HCFS[1:0] 0 R/W 22 14 6 0 R/W Table 38: Bit 31 to 11 10 HcControl register: bit description Symbol RWE Description reserved RemoteWakeupEnable: This bit is used by the HCD to enable or disable the remote wake-up feature on detecting upstream resume signaling. When this bit and the ResumeDetected (RD) bit in HcInterruptStatus are set, a remote wake-up is signaled to the host system. Setting this bit has no impact on the generation of hardware interrupt. RemoteWakeupConnected: This bit indicates whether the HC supports remote wake-up signaling. If remote wake-up is supported and used by the system, it is the responsibility of the system firmware to set this bit during POST. The HC clears the bit upon a hardware reset but does not alter it upon a software reset. Remote wake-up signaling of the host system is host-bus-specific and is not described in this specification. reserved HostControllerFunctionalState for USB 00 -- USBReset 01 -- USBResume 10 -- USBOperational 11 -- USBSuspend A transition to USBOperational from another state causes start-of-frame (SOF) generation to begin 1 ms later. The HCD may determine whether the HC has begun sending SOFs by reading the StartofFrame (SF) field of HcInterruptStatus. This field may be changed by the HC only when it is in the USBSuspend state. The HC may move from the USBSuspend state to the USBResume state after detecting the resume signaling from a downstream port. The HC enters USBReset after a software reset and a hardware reset. The latter also resets the Root Hub and asserts subsequent reset signaling to downstream ports. 9 RWC 8 7 to 6 HCFS[1:0] 5 to 0 9397 750 12337 - reserved (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 72 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.1.3 HcCommandStatus register (R/W: 02H/82H) The HcCommandStatus register is a 4-byte register, and the bit allocation is given in Table 39. This register is used by the HC to receive commands issued by the HCD, and it also reflects the current status of the HC. To the HCD, it appears to be a `write to set' register. The HC must ensure that bits written as logic 1 become set in the register while bits written as logic 0 remain unchanged in the register. The HCD may issue multiple distinct commands to the HC without concern for corrupting previously issued commands. The HCD has normal read access to all bits. The SchedulingOverrunCount (SOC) field indicates the number of frames with which the HC has detected the scheduling overrun error. This occurs when the Periodic list does not complete before the End-of-Frame (EOF). When a scheduling overrun error is detected, the HC increments the counter and sets the SchedulingOverrun (SO) field of the HcInterruptStatus register. Code (Hex): 02 -- read Code (Hex): 82 -- write Table 39: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcCommandStatus register: bit allocation 31 23 15 7 30 22 14 6 29 21 reserved 13 5 12 reserved 4 reserved 3 2 1 0 HCR 0 R/W 11 10 0 R 9 28 reserved 20 19 18 17 SOC[1:0] 0 R 8 16 27 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 73 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcCommandStatus register: bit description Symbol SOC[1:0] Description reserved SchedulingOverrunCount: This field is incremented on each scheduling overrun error. It is initialized to 00B and wraps around at 11B. It needs to be incremented when a scheduling overrun is detected even if SchedulingOverrun in HcInterruptStatus has already been set. This is used by the HCD to monitor any persistent scheduling problems. reserved HostControllerReset: This bit is set by the HCD to initiate a software reset of the HC. Regardless of the functional state of the HC, it moves to the USBSuspend state in which most of the operational registers are reset except those stated otherwise. This bit is cleared by the HC on completing the reset operation. The reset operation must be completed within 10 ms. This bit, when set, should not cause a reset to the Root Hub and no subsequent reset signaling should be asserted to its downstream ports. Table 40: Bit 31 to 18 17 to 16 15 to 1 0 HCR 15.1.4 HcInterruptStatus register (R/W: 03H/83H) This register (bit allocation: Table 41) provides the status of the events that cause hardware interrupts. When an event occurs, the HC sets the corresponding bit in this register. When a bit is set, a hardware interrupt is generated if the interrupt is enabled in the HcInterruptEnable register (see Section 15.1.5) and the MasterInterruptEnable (MIE) bit is set. The HCD may clear specific bits in this register by writing logic 1 to the bit positions to be cleared. The HC, however, does not clear the bit. The HCD may not set any of these bits. Code (Hex): 03 -- read Code (Hex): 83 -- write Table 41: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 9397 750 12337 HcInteruptStatus register: bit allocation 31 23 15 7 reserved 30 22 14 6 RHSC 0 R/W 29 21 13 5 FNO 0 R/W 28 reserved 20 reserved 12 reserved 4 UE 0 R/W 3 RD 0 R/W 2 SF 0 R/W 1 reserved 0 SO 0 R/W 11 10 9 8 19 18 17 16 27 26 25 24 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 74 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcInterruptStatus register: bit description Symbol RHSC Description reserved RootHubStatusChange: This bit is set when the content of HcRhStatus or the content of any of HcRhPortStatus[NumberofDownstreamPort] has changed. FrameNumberOverflow: This bit is set when the MSB of HcFmNumber (bit 15) changes from logic 0 to 1 or from logic 1 to 0. UnrecoverableError: This bit is set when the HC detects a system error not related to the USB. The HC should not proceed with any processing nor signaling before the system error has been corrected. The HCD clears this bit after the HC has been reset. Philips Host Controller Interface (PHCI): Always set to logic 0. ResumeDetected: This bit is set when the HC detects that a device on the USB is asserting resume signaling. It is the transition from no resume signaling to resume signaling causing this bit to be set. This bit is not set when the HCD sets the USBResume state. StartOfFrame: At the start of each frame, this bit is set by the HC and an SOF is generated. reserved SchedulingOverrun: This bit is set when the USB schedules for current frame overruns. A scheduling overrun also causes the SchedulingOverrunCount (SOC) of HcCommandStatus to be incremented. Table 42: Bit 31 to 7 6 5 FNO 4 UE 3 RD 2 1 0 SF SO 15.1.5 HcInterruptEnable register (R/W: 04H/84H) Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register is used to control which events generate a hardware interrupt. When the following three conditions occur: * A bit is set in the HcInterruptStatus register * The corresponding bit in the HcInterruptEnable register is set * The MasterInterruptEnable (MIE) bit is set. Then, a hardware interrupt is requested on the host bus. Writing logic 1 to a bit in the HcInterruptEnable register sets the corresponding bit, whereas writing logic 0 to a bit in this register leaves the corresponding bit unchanged. On a read, the current value of this register is returned. Table 43 contains the bit allocation of the register. Code (Hex): 04 -- read Code (Hex): 84 -- write 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 75 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 43: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcInterruptEnable register: bit allocation 31 MIE 0 R/W 23 15 7 reserved 22 14 6 RHSC 0 R/W Table 44: Bit 31 21 13 5 FNO 0 R/W 20 reserved 12 reserved 4 UE 0 R/W 3 RD 0 R/W 2 SF 0 R/W 1 reserved 0 SO 0 R/W 11 10 9 8 30 29 28 27 reserved 19 18 17 16 26 25 24 HcInterruptEnable register: bit description Symbol MIE Description MasterInterruptEnable by the HCD: Logic 0 is ignored by the HC. Logic 1 enables interrupt generation by events specified in other bits of this register. reserved 0 -- ignore 1 -- enable interrupt generation because of Root Hub Status Change 30 to 7 6 RHSC 5 FNO 0 -- ignore 1 -- enable interrupt generation because of Frame Number Overflow 4 3 2 1 0 UE RD SF SO 0 -- ignore 1 -- enable interrupt generation because of Unrecoverable Error 0 -- ignore 1 -- enable interrupt generation because of Resume Detect 0 -- ignore 1 -- enable interrupt generation because of Start of Frame reserved 0 -- ignore 1 -- enable interrupt generation because of Scheduling Overrun 15.1.6 HcInterruptDisable register (R/W: 05H/85H) Each disable bit in the HcInterruptDisable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptDisable register is coupled with the HcInterruptEnable register. Thus, writing logic 1 to a bit in this register clears the corresponding bit in the HcInterruptEnable register, whereas 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 76 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller writing logic 0 to a bit in this register leaves the corresponding bit in the HcInterruptEnable register unchanged. On a read, the current value of the HcInterruptEnable register is returned. Table 45 provides the bit allocation of the HcInterruptDisable register. Code (Hex): 05 -- read Code (Hex): 85 -- write Table 45: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 7 reserved 6 RHSC 0 R/W Table 46: Bit 31 5 FNO 0 R/W 4 UE 0 R/W 15 14 13 12 reserved 3 RD 0 R/W 2 SF 0 R/W 1 reserved 0 SO 0 R/W HcInterruptDisable register: bit allocation 31 MIE 0 R/W 23 22 21 20 reserved 11 10 9 8 30 29 28 27 reserved 19 18 17 16 26 25 24 HcInterruptDisable register: bit description Symbol MIE Description Logic 0 is ignored by the HC. Logic 1 disables interrupt generation because of events specified in other bits of this register. This field is set after a hardware or software reset. reserved 0 -- ignore 1 -- disable interrupt generation because of Root Hub Status Change 30 to 7 6 RHSC 5 FNO 0 -- ignore 1 -- disable interrupt generation because of Frame Number Overflow 4 3 UE RD 0 -- ignore 1 -- disable interrupt generation because of Unrecoverable Error 0 -- ignore 1 -- disable interrupt generation because of Resume Detect 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 77 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcInterruptDisable register: bit description...continued Symbol SF SO Description 0 -- ignore 1 -- disable interrupt generation because of Start of Frame reserved 0 -- ignore 1 -- disable interrupt generation because of Scheduling Overrun Table 46: Bit 2 1 0 15.2 HC Frame Counter registers 15.2.1 HcFmInterval register (R/W: 0DH/8DH) The HcFmInterval register (bit allocation: Table 47) contains a 14-bit value that indicates the bit time interval in a frame between two consecutive SOFs. In addition, it contains a 15-bit value indicating the full-speed maximum packet size that the HC may transmit or receive without causing a scheduling overrun. The HCD may carry out minor adjustments on FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for the HC to synchronize with an external clocking resource and to adjust any unknown local clock offset. Code (Hex): 0D -- read Code (Hex): 8D -- write Table 47: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 1 R/W 1 R/W 0 R/W 1 R/W 7 0 R/W 15 reserved 6 1 R/W 5 0 R/W 4 FI[7:0] 1 R/W 1 R/W 1 R/W 1 R/W 1 R/W 3 0 R/W 14 0 R/W 13 0 R/W 12 HcFmInterval register: bit allocation 31 FIT 0 R/W 23 0 R/W 22 0 R/W 21 0 R/W 20 30 29 28 27 FSMPS[14:8] 0 R/W 19 0 R/W 11 FI[13:8] 1 R/W 2 1 R/W 1 0 R/W 0 0 R/W 18 0 R/W 10 0 R/W 17 0 R/W 9 0 R/W 16 0 R/W 8 26 25 24 FSMPS[7:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 78 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcFmInterval register: bit description Symbol FIT FSMPS [14:0] Description FrameIntervalToggle: The HCD toggles this bit whenever it loads a new value to FrameInterval. FSLargestDataPacket: Specifies a value that is loaded into the Largest Data Packet Counter at the beginning of each frame. The counter value represents the largest amount of data in bits that can be sent or received by the HC in a single transaction at any given time without causing a scheduling overrun. The field value is calculated by the HCD. reserved FrameInterval: Specifies the interval between two consecutive SOFs in bit times. The nominal value is set to 11999. The HCD must store the current value of this field before resetting the HC. Setting the HostControllerReset (HCR) field of the HcCommandStatus register causes the HC to reset this field to its nominal value. The HCD may choose to restore the stored value upon completing the Reset sequence. Table 48: Bit 31 30 to 16 15 to 14 13 to 0 FI[13:0] 15.2.2 HcFmRemaining register (R/W: 0EH/8EH) The HcFmRemaining register is a 14-bit down counter showing the bit time remaining in the current frame. The bit allocation is given in Table 49. Code (Hex): 0E -- read Code (Hex): 8E -- write Table 49: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcFmRemaining register: bit allocation 31 FRT 0 R/W 23 15 reserved 7 0 R/W 6 0 R/W 0 R/W 5 0 R/W 0 R/W 4 FR[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 3 22 14 21 13 20 reserved 12 11 FR[13:8] 0 R/W 2 0 R/W 1 0 R/W 0 10 9 8 30 29 28 27 reserved 19 18 17 16 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 79 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcFmRemaining register: bit description Symbol FRT Description FrameRemainingToggle: This bit is loaded from the FrameIntervalToggle (FIT) field of HcFmInterval whenever FrameRemaining (FR) reaches 0. This bit is used by the HCD for synchronization between FrameInterval (FI) and FrameRemaining (FR). reserved FrameRemaining: This counter is decremented at each bit time. When it reaches zero, it is reset by loading the FrameInterval (FI) value specified in HcFmInterval at the next bit time boundary. When entering the USBOperational state, the HC reloads it with the content of the FrameInterval (FI) part of the HcFmInterval register and uses the updated value from the next SOF. Table 50: Bit 31 30 to 14 13 to 0 FR[13:0] 15.2.3 HcFmNumber register (R/W: 0FH/8FH) The HcFmNumber register is a 16-bit counter, and the bit allocation is given in Table 51. It provides a timing reference for events happening in the HC and the HCD. The HCD may use the 16-bit value specified in this register and generate a 32-bit frame number without requiring frequent access to the register. Code (Hex): 0F -- read Code (Hex): 8F -- write Table 51: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HCFmNumber register: bit allocation 31 23 15 0 R 7 0 R 30 22 14 0 R 6 0 R 29 21 13 0 R 5 0 R 28 reserved 20 reserved 12 FN[15:8] 0 R 4 FN[7:0] 0 R 0 R 0 R 0 R 0 R 0 R 3 0 R 2 0 R 1 0 R 0 11 10 9 8 19 18 17 16 27 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 80 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcFmNumber register: bit description Symbol - FN[15:0] Description reserved FrameNumber: This is incremented when HcFmRemaining is reloaded. It needs to be rolled over to 0H after FFFFH. When the USBOperational state is entered, this is incremented automatically. The content needs to be written to HCCA after the HC has incremented the FrameNumber (FN) at each frame boundary and sent an SOF. However, the content needs to be written before the HC reads the first Endpoint Descriptor (ED) in that frame. After writing to HCCA, the HC needs to set the StartofFrame (SF) in HcInterruptStatus. Table 52: Bit 31 to 16 15 to 0 15.2.4 HcLSThreshold register (R/W: 11H/91H) The HcLSThreshold register contains an 11-bit value used by the HC to determine whether to commit to the transfer of a maximum of 8-byte LS packet before the EOF. Neither the HC nor the HCD is allowed to change this value. Table 53 shows the bit allocation of the register. Code (Hex): 11 -- read Code (Hex): 91 -- write Table 53: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcLSThreshold register: bit allocation 31 23 15 7 0 R/W 30 22 14 6 0 R/W Table 54: Bit 31 to 11 10 to 0 29 21 13 reserved 5 1 R/W 4 LST[7:0] 0 R/W 1 R/W 0 R/W 0 R/W 0 R/W 3 1 R/W 2 28 reserved 20 reserved 12 11 10 9 LST[10:8] 1 R/W 1 0 R/W 0 8 19 18 17 16 27 26 25 24 HcLSThreshold register: bit description Symbol - LST[10:0] Description reserved LSThreshold: Contains a value that is compared to the FrameRemaining (FR) field before a low-speed transaction is initiated. The transaction is started only if FrameRemaining (FR) this field. The value is calculated by the HCD, which considers transmission and set-up overhead. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 Product data Rev. 03 -- 06 January 2004 81 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.3 HC Root Hub registers All registers included in this partition are dedicated to the USB Root Hub, which is an integral part of the HC although it is a functionally a separate entity. The HCD emulates USB Driver (USBD) accesses to the Root Hub by using a register interface. The HCD maintains many USB-defined hub features that are not required to be supported in hardware. For example, the Hub's device, Configuration, Interface and Endpoint Descriptors are maintained only in the HCD, as well as some static fields of the Class Descriptor. The HCD also maintains and decodes the address of the Root Hub device and other trivial operations that are better suited to software than to hardware. Root Hub registers are developed to maintain the similarity of bit organization and operation to typical hubs found in the system. Four registers are defined as follows: * * * * HcRhDescriptorA HcRhDescriptorB HcRhStatus HcRhPortStatus[1:NDP]. Each register is read and written as a DWord. These registers are only written during initialization to correspond with the system implementation. The HcRhDescriptorA and HcRhDescriptorB registers should be implemented such that they are writeable, regardless of the USB states of the HC. HcRhStatus and HcRhPortStatus must be writeable during the USBOperational state. 15.3.1 HcRhDescriptorA register (R/W: 12H/92H) The HcRhDescriptorA register is the first register of two describing the characteristics of the Root Hub. The bit allocation is given in Table 55. Code (Hex): 12 -- read Code (Hex): 92 -- write Table 55: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 15 14 reserved 13 12 NOCP 0 R/W 1 R/W 23 1 R/W 22 1 R/W 21 HcRhDescriptorA register: bit description 31 30 29 28 1 R/W 20 reserved 11 OCPM 1 R/W 10 DT 0 R 9 NPS 0 R/W 8 PSM 1 R/W 27 1 R/W 19 26 1 R/W 18 25 1 R/W 17 24 1 R/W 16 POTPGT[7:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 82 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 5 reserved 4 3 2 1 NDP[1:0] 1 R 0 R 0 Bit Symbol Reset Access 7 - 6 Table 56: Bit 31 to 24 HcRhDescriptorA register: bit description Symbol Description POTPGT PowerOnToPowerGoodTime: This byte specifies the duration HCD [7:0] has to wait before accessing a powered-on port of the Root Hub. It is implementation-specific (IS). The unit of time is 2 ms. The duration is calculated as POTPGT x 2 ms. NOCP reserved NoOverCurrentProtection: This bit describes how the overcurrent status for the Root Hub ports are reported. When this bit is cleared, the OverCurrentProtectionMode (OCPM) field specifies global or per-port reporting. 0 -- overcurrent status is collectively reported for all downstream ports 1 -- no overcurrent reporting supported 23 to 13 12 11 OCPM OverCurrentProtectionMode: This bit describes how the overcurrent status for the Root Hub ports are reported. At reset, this field should reflect the same mode as PowerSwitchingMode. This field is valid only if the NoOverCurrentProtection (NOCP) field is cleared. 0 -- overcurrent status is reported collectively for all downstream ports 1 -- overcurrent status is reported on a per-port basis. On power up, clear this bit and then set it to logic 1 10 9 DT NPS DeviceType: This bit specifies that the Root Hub is not a compound device; it is not permitted. This field should always read as 0. NoPowerSwitching: This bit is used to specify whether power switching is supported or ports are always powered. It is implementation specific. When this bit is cleared, the PowerSwitchingMode (PSM) bit specifies global or per-port switching. 0 -- ports are power switched 1 -- ports are always powered on when the HC is powered on 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 83 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcRhDescriptorA register: bit description...continued Symbol PSM Description PowerSwitchingMode: This bit is used to specify how the power switching of the Root Hub ports is controlled. It is implementation specific. This field is valid only if the NoPowerSwitching (NPS) field is cleared. 0 -- all ports are powered at the same time 1 -- each port is individually powered. This mode allows port power to be controlled by either the global switch or per-port switching. If the PortPowerControlMask (PPCM) bit is set, the port responds to only port power commands (Set/ClearPortPower). If the port mask is cleared, then the port is controlled only by the global power switch (Set/ClearGlobalPower). Table 56: Bit 8 7 to 2 1 to 0 - reserved NDP[1:0] NumberDownstreamPorts: These bits specify the number of downstream ports supported by the Root Hub. It is implementation specific. The maximum number of ports supported is 2. 15.3.2 HcRhDescriptorB register (R/W: 13H/93H) The HcRhDescriptorB register is the second register of two describing the characteristics of the Root Hub. These fields are written during initialization to correspond with the system implementation. Reset values are implementation specific. Table 57 shows the bit allocation of the register. Code (Hex): 13 -- read Code (Hex): 93 -- write Table 57: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcRhDescriptorB register: bit allocation 31 23 15 7 30 22 14 6 29 21 reserved 13 5 reserved R/W 12 reserved 4 3 2 1 DR[2:0] IS R/W R/W 0 11 R/W 10 28 reserved 20 19 18 17 PPCM[2:0] IS R/W 9 R/W 8 16 27 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 84 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcRhDescriptorB register: bit description Symbol PPCM[2:0] Description reserved PortPowerControlMask: Each bit indicates whether a port is affected by a global power control command when PowerSwitchingMode is set. When set, the power state of the port is only affected by per-port power control (Set/ClearPortPower). When cleared, the port is controlled by the global power switch (Set/ClearGlobalPower). If the device is configured to global switching mode (PowerSwitchingMode = 0), this field is not valid. Bit 2 -- Ganged-power mask on port 2 Bit 1 -- Ganged-power mask on port 1 Bit 0 -- reserved Table 58: Bit 31 to 19 18 to 16 15 to 3 2 to 0 DR[2:0] reserved DeviceRemovable: Each bit is dedicated to a port of the Root Hub. When cleared, the attached device is removable. When set, the attached device is not removable. Bit 2 -- Device attached to port 2 Bit 1 -- Device attached to port 1 Bit 0 -- reserved 15.3.3 HcRhStatus register (R/W: 14H/94H) The HcRhStatus register is divided into two parts. The lower word of a DWord represents the Hub Status field and the upper word represents the Hub Status Change field. Reserved bits should always be written as logic 0. See Table 59 for bit allocation of the register. Code (Hex): 14 -- read Code (Hex): 94 -- write Table 59: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcRhStatus register: bit allocation 31 CRWE 0 W 23 15 DRWE 0 R/W 22 14 21 reserved 13 12 11 reserved 10 20 30 29 28 27 reserved 19 18 17 CCIC 0 R/W 9 16 LPSC 0 R/W 8 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 85 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 5 reserved 4 3 2 1 OCI 0 R 0 LPS 0 R/W Bit Symbol Reset Access 7 - 6 Table 60: Bit 31 HcRhStatus register: bit description Symbol CRWE Description On write--ClearRemoteWakeupEnable: Writing logic 1 clears DeviceRemoveWakeupEnable (DRWE). Writing logic 0 has no effect. reserved OverCurrentIndicatorChange: This bit is set by hardware when a change has occurred to the OverCurrentIndicator (OCI) field of this register. The HCD clears this bit by writing logic 1. Writing logic 0 has no effect. On read--LocalPowerStatusChange: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write--SetGlobalPower: In the global power mode (PowerSwitchingMode = 0), logic 1 is written to this bit to turn on power to all ports (clear PortPowerStatus). In the per-port power mode, it sets PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. 30 to 18 17 CCIC 16 LPSC 15 DRWE On read--DeviceRemoteWakeupEnable: This bit enables the bit ConnectStatusChange as a resume event, causing a state transition from USBSuspend to USBResume and setting the ResumeDetected interrupt. 0 -- ConnectStatusChange is not a remote wake-up event 1 -- ConnectStatusChange is a remote wake-up event On write--SetRemoteWakeupEnable: Writing logic 1 sets DeviceRemoveWakeupEnable. Writing logic 0 has no effect. 14 to 2 1 OCI reserved OverCurrentIndicator: This bit reports overcurrent conditions when global reporting is implemented. When set, an overcurrent condition exists. When cleared, all power operations are normal. If per-port overcurrent protection is implemented, this bit is always logic 0. On read--LocalPowerStatus: The Root Hub does not support the local power status feature. Therefore, this bit is always read as logic 0. On write--ClearGlobalPower: In the global power mode (PowerSwitchingMode = 0), logic 1 is written to this bit to turn off power to all ports (clear PortPowerStatus). In the per-port power mode, it clears PortPowerStatus only on ports whose PortPowerControlMask bit is not set. Writing logic 0 has no effect. 0 LPS 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 86 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.3.4 HcRhPortStatus[1:2] register (R/W [1]: 15H/95H; [2]: 16H/96H) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port basis. NumberDownstreamPorts represents the number of HcRhPortStatus registers that are implemented in hardware. The lower word is used to reflect the port status, whereas the upper word reflects the status change bits. Some status bits are implemented with special write behavior. If a transaction (token through handshake) is in progress when a write to change port status occurs, the resulting port status change must be postponed until the transaction completes. Reserved bits should always be written logic 0. The bit allocation of the HcRhPortStatus[1:2] register is given in Table 61. Code (Hex): [1] = 15, [2] = 16 -- read Code (Hex): [1] = 95, [2] = 96 -- write Table 61: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcRhPortStatus[1:2] register: bit allocation 31 23 15 7 30 22 reserved 14 6 reserved 13 reserved 5 4 PRS 0 R/W 3 POCI 0 R/W 2 PSS 0 R/W 29 21 28 reserved 20 PRSC 0 R/W 12 19 OCIC 0 R/W 11 18 PSSC 0 R/W 10 17 PESC 0 R/W 9 LSDA 0 R/W 1 PES 0 R/W 16 CSC 0 R/W 8 PPS 0 R/W 0 CCS 0 R/W 27 26 25 24 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 87 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcRhPortStatus[1:2] register: bit description Symbol PRSC Description reserved PortResetStatusChange: This bit is set at the end of the 10 ms port reset signal. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- port reset is not complete 1 -- port reset is complete Table 62: Bit 31 to 21 20 19 OCIC PortOverCurrentIndicatorChange: This bit is valid only if overcurrent conditions are reported on a per-port basis. This bit is set when the Root Hub changes the PortOverCurrentIndicator (POCI) bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no change in PortOverCurrentIndicator (POCI) 1 -- PortOverCurrentIndicator (POCI) has changed 18 PSSC PortSuspendStatusChange: This bit is set when the full resume sequence is complete. This sequence includes the 20 ms resume pulse, LS EOP and 3 ms re-synchronization delay. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. This bit is also cleared when ResetStatusChange is set. 0 -- resume is not completed 1 -- resume is completed 17 PESC PortEnableStatusChange: This bit is set when hardware events cause the PortEnableStatus (PES) bit to be cleared. Changes from the HCD writes do not set this bit. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. 0 -- no change in PortEnableStatus (PES) 1 -- change in PortEnableStatus (PES) 16 CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD can write logic 1 to clear this bit. Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared when a SetPortReset, SetPortEnable or SetPortSuspend write occurs, this bit is set to force the driver to re-evaluate the connection status because these writes should not occur if the port is disconnected. 0 -- no change in CurrentConnectStatus (CCS) 1 -- change in CurrentConnectStatus (CCS) Remark: If the DeviceRemovable[NDP] bit is set, this bit is set only after a Root Hub reset to inform the system that the device is attached. 15 to 10 - reserved 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 88 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcRhPortStatus[1:2] register: bit description...continued Symbol LSDA Description On read--LowSpeedDeviceAttached: This bit indicates the speed of the device attached to this port. When set, a low-speed device is attached to this port. When cleared, a full-speed device is attached to this port. This field is valid only when CurrentConnectStatus (CCS) is set. 0 -- full-speed device attached 1 -- low-speed device attached On write--ClearPortPower: The HCD clears the PortPowerStatus (PPS) bit by writing logic 1 to this bit. Writing logic 0 has no effect. Table 62: Bit 9 8 PPS On read--PortPowerStatus: This bit reflects the port power status, regardless of the type of power switching implemented. This bit is cleared if an overcurrent condition is detected. The HCD sets this bit by writing SetPortPower or SetGlobalPower. The HCD clears this bit by writing ClearPortPower or ClearGlobalPower. PowerSwitchingMode (PCM) and PortPowerControlMask[NDP] (PPCM[NDP]) determine which power control switches are enabled. In the global switching mode (PowerSwitchingMode = 0), only the Set/ClearGlobalPower command controls this bit. In the per-port power switching (PowerSwitchingMode = 1), if the PortPowerControlMask[NDP] (PPCM[NDP]) bit for the port is set, only Set/ClearPortPower commands are enabled. If the mask is not set, only Set/ClearGlobalPower commands are enabled. When port power is disabled, CurrentConnectStatus (CCS), PortEnableStatus (PES), PortSuspendStatus (PSS) and PortResetStatus (PRS) should be reset. 0 -- port power is OFF 1 -- port power is ON On write--SetPortPower: The HCD writes logic 1 to set the PortPowerStatus (PPS) bit. Writing logic 0 has no effect. Remark: This bit always reads logic 1 if power switching is not supported. 7 to 5 - reserved 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 89 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcRhPortStatus[1:2] register: bit description...continued Symbol PRS Description On read--PortResetStatus: When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is completed, this bit is cleared when PortResetStatusChange (PRSC) is set. This bit cannot be set if CurrentConnectStatus (CCS) is cleared. 0 -- port reset signal is not active 1 -- port reset signal is active On write--SetPortReset: The HCD sets the port reset signaling by writing logic 1 to this bit. Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared, this write does not set PortResetStatus (PRS) but instead sets ConnectStatusChange (CSC). This informs the driver that it attempted to reset a disconnected port. Table 62: Bit 4 3 POCI On read--PortOverCurrentIndicator: This bit is valid only when the Root Hub is configured in such a way that overcurrent conditions are reported on a per-port basis. If per-port overcurrent reporting is not supported, this bit is set to logic 0. If cleared, all power operations are normal for this port. If set, an overcurrent condition exists on this port. This bit always reflects the overcurrent input signal 0 -- no overcurrent condition 1 -- overcurrent condition detected On write--ClearSuspendStatus: The HCD writes logic 1 to initiate a resume. Writing logic 0 has no effect. A resume is initiated only if PortSuspendStatus (PSS) is set. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 90 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcRhPortStatus[1:2] register: bit description...continued Symbol PSS Description On read--PortSuspendStatus: This bit indicates whether the port is suspended or is in the resume sequence. It is set by a SetSuspendState write and cleared when PortSuspendStatusChange (PSSC) is set at the end of the resume interval. This bit cannot be set if CurrentConnectStatus (CCS) is cleared. This bit is also cleared when PortResetStatusChange (PRSC) is set at the end of the port reset or when the HC is placed in the USBResume state. If an upstream resume is in progress, it should propagate to the HC. 0 -- port is not suspended 1 -- port is suspended On write--SetPortSuspend: The HCD sets the PortSuspendStatus (PSS) bit by writing logic 1 to this bit. Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared, this write does not set PortSuspendStatus (PSS); instead it sets ConnectStatusChange (CSC). This informs the driver that it attempted to suspend a disconnected port. Table 62: Bit 2 1 PES On read--PortEnableStatus: This bit indicates whether the port is enabled or disabled. The Root Hub may clear this bit when an overcurrent condition, disconnect event, switched-off power or operational bus error, such as babble, is detected. This change also causes PortEnabledStatusChange to be set. The HCD sets this bit by writing SetPortEnable and clears it by writing ClearPortEnable. This bit cannot be set when CurrentConnectStatus (CCS) is cleared. This bit is also set, if it is not already, at the completion of a port reset when ResetStatusChange is set or port suspend when SuspendStatusChange is set. 0 -- port is disabled 1 -- port is enabled On write--SetPortEnable: The HCD sets PortEnableStatus (PES) by writing logic 1. Writing logic 0 has no effect. If CurrentConnectStatus (CCS) is cleared, this write does not set PortEnableStatus (PES), but instead sets ConnectStatusChange (CSC). This informs the driver that it attempted to enable a disconnected port. 0 CCS On read--CurrentConnectStatus: This bit reflects the current state of the downstream port. 0 -- no device connected 1 -- device connected On write--ClearPortEnable: The HCD writes logic 1 to this bit to clear the PortEnableStatus (PES) bit. Writing logic 0 has no effect. CurrentConnectStatus (CSC) is not affected by any write. Remark: This bit always reads 1B when the attached device is nonremovable (DeviceRemoveable[NDP]). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 91 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.4 HC DMA and interrupt control registers 15.4.1 HcHardwareConfiguration register (R/W: 20H/A0H) The bit allocation of the HcHardwareConfiguration register is given in Table 63. Code (Hex): 20 -- read Code (Hex): A0 -- write Table 63: Bit Symbol HcHardwareConfiguration register: bit allocation 15 Disable Suspend_ Wakeup 0 R/W 7 OneDMA 14 Global Power Down 0 R/W 6 DACKInput Polarity 0 R/W Table 64: Bit 15 13 Connect PullDown _DS2 0 R/W 5 DREQ Output Polarity 1 R/W 12 Connect PullDown _DS1 0 R/W 4 11 Suspend ClkNotStop 0 R/W 3 10 AnalogOC Enable 0 R/W 2 Interrupt Output Polarity 0 R/W 9 OneINT 8 DACKMode Reset Access Bit Symbol 0 R/W 1 Interrupt PinTrigger 0 R/W 0 R/W 0 InterruptPin Enable 0 R/W DataBusWidth[1:0] Reset Access 0 R/W 0 R/W 1 R/W HcHardwareConfiguration register: bit description Symbol Description DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the D_SUSPEND/D_WAKEUP and H_SUSPEND/H_WAKEUP pins. Therefore, these pins will always remain HIGH and pulling them LOW does not wake up the HC and the DC. GlobalPowerDown ConnectPullDown_DS2 Set this bit to logic 1 to reduce power consumption of the OTG ATX in the suspend mode. 0 -- disconnect built-in pull-down resistors on H_DM2 and H_DP2 1 -- connect built-in pull-down resistors on H_DM2 and H_DP2 for the downstream port 2 Remark: Port 2 is always used as a host port. 14 13 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 92 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcHardwareConfiguration register: bit description...continued Symbol ConnectPullDown_DS1 Description 0 -- disconnect built-in pull-down resistors on OTG_DM1 and OTG_DP1 1 -- connect built-in pull-down resistors on OTG_DM1 and OTG_DP1 Remark: This bit is effective only when port 1 is configured as the host port (the OTGMODE pin is HIGH, and the ID pin is LOW). When port 1 is configured as the OTG port, (the OTGMODE pin is LOW), the pull-down resistors on OTG_DM1 and OTG_DP1 are controlled by the LOC_PULL_DN_DP and LOC_PULL_DN_DM bits of the OtgControl register. Table 64: Bit 12 11 10 9 SuspendClkNotStop AnalogOCEnable OneINT 0 -- clock can be stopped when suspended 1 -- clock cannot be stopped when suspended 0 -- use external OC detection; digital input 1 -- use on-chip OC detection; analog input 0 -- HC interrupt routed to INT1, DC interrupt routed to INT2 1 -- HC and DC interrupts routed to INT1 only, INT2 is unused 8 DACKMode 0 -- normal operation; DACK1 is used with read and write signals; power-up value 1 -- reserved 0 -- HC DMA request and acknowledge routed to DREQ1 and DACK1, DC DMA request and acknowledge routed to DREQ2 and DACK2 1 -- HC and DC DMA requests and acknowledges routed to DREQ1 and DACK1; DREQ2 and DACK2 unused 7 OneDMA 6 5 4 to 3 2 1 0 DACKInputPolarity DREQOutputPolarity DataBusWidth[1:0] InterruptOutputPolarity InterruptPinTrigger InterruptPinEnable 0 -- DACK1 is active LOW; power-up value 1 -- DACK1 is active HIGH 0 -- DREQ1 is active LOW 1 -- DREQ1 is active HIGH; power-up value 01 -- microprocessor interface data bus width is 16 bits Others -- reserved 0 -- INT1 interrupt is active LOW; power-up value 1 -- INT1 interrupt is active HIGH 0 -- INT1 interrupt is level-triggered; power-up value 1 -- INT1 interrupt is edge-triggered 0 -- power-up value 1 -- global interrupt pin INT1 is enabled; this bit should be used with the HcPInterruptEnable register to enable pin INT1 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 93 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.4.2 HcDMAConfiguration register (R/W: 21H/A1H) Table 65 contains the bit allocation of the HcDMAConfiguration register. Code (Hex): 21 -- read Code (Hex): A1 -- write Table 65: Bit Symbol Reset Access Bit Symbol Reset Access HcDMAConfiguration register: bit allocation 15 7 DMACounter Enable 0 R/W 14 6 13 5 12 reserved 4 DMA Enable 0 R/W 0 R/W 3 2 Buffer_Type_Select[2:0] 0 R/W 0 R/W 1 0 DMARead WriteSelect 0 R/W 11 10 9 8 BurstLen[1:0] 0 R/W Table 66: Bit 15 to 8 7 0 R/W HcDMAConfiguration register: bit description Symbol DMACounterEnable Description reserved 0 -- reserved 1 -- DMA counter is enabled. Once the counter is enabled, the HCD must initialize the HcTransferCounter register to a non-zero value for DREQ to be raised after the DMAEnable bit is set to HIGH. 6 to 5 BurstLen[1:0] 00 -- single-cycle burst DMA 01 -- 4-cycle burst DMA 10 -- 8-cycle burst DMA 11 -- reserved I/O bus with 32-bit data path width supports only single and four cycle DMA burst. 4 DMAEnable 0 -- DMA is disabled 1 -- DMA is enabled This bit needs to be reset when the DMA transfer is completed. 3 to 1 Buffer_Type_Select [2:0] Bit 3 0 0 0 0 1 Bit 2 0 0 1 1 X Bit 1 0 1 0 1 X Buffer Type ISTL0 (default) ISTL1 INTL ATL Direct Addressing 0 DMAReadWriteSelect 0 -- read from the buffer memory of the HC 1 -- write to the buffer memory of the HC 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 94 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 15.4.3 HcTransferCounter register (R/W: 22H/A2H) Regardless of the programmed I/O (PIO) or DMA data transfer modes, this register is used to initialize the number of bytes to be transferred to or from the ISTL, INTL or ATL buffer RAM. For the count value loaded in the register to take effect, the HCD is required to set bit 7 of the HcDMAConfiguration register to HIGH. When the count value has reached, the HC needs to generate an internal EOT signal to set bit 2 of the HcPInterrupt register, AllEOInterrupt, and update the HcBufferStatus register. The bit allocation of the HcTransferCounter register is given in Table 67. Code (Hex): 22 -- read Code (Hex): A2 -- write Table 67: Bit 15 to 0 HcTransferCounter register: bit description Symbol CounterValue [15:0] Access R/W Value 0000H Description Number of data bytes to be read from or written to the buffer RAM. 15.4.4 HcPInterrupt register (R/W: 24H/A4H) All the bits in this register are active at power-on reset. None of the active bits, however, will cause an interrupt on the interrupt pin (INT1) unless they are set by the respective bits in the HcPInterruptEnable register and bit 0 of the HcHardwareConfiguration register is also set. After this register (24H-read) is read, the bits that are active will not be reset until logic 1 is written to the bits in this register (A4H-write) to clear it. The bits in this register are cleared only when you write to this register indicating the bits to be cleared. To clear all the enabled bits in this register, the HCD must write FFH to this register. The bit allocation of the HcPInterrupt register is given in Table 68. Code (Hex): 24 -- read Code (Hex): A4 -- write Table 68: Bit Symbol Reset Access Bit Symbol Reset Access HcPInterrupt register: bit allocation 15 7 INTL_IRQ 0 R/W 14 6 ClkReady 0 R/W 13 reserved 5 HC Suspended 0 R/W 4 OPR_Reg 0 R/W 3 AllEOT Interrupt 0 R/W 2 ISTL_1_ INT 0 R/W 12 11 10 9 OTG_IRQ 0 R/W 1 ISTL_0_ INT 0 R/W 8 ATL_IRQ 0 R/W 0 SOF_INT 0 R/W 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 95 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcPInterrupt register: bit description Symbol OTG_IRQ Description reserved 0 -- no event 1 -- The OTG interrupt event needs to read the OtgInterrupt register to get the cause of the interrupt. Table 69: Bit 15 to 10 9 8 ATL_IRQ 0 -- no event 1 -- Count value of the HcATLDoneThresholdCount register or the time-out value of the HcATLPTDDoneThresholdTimeOut register has reached. The microprocessor is required to read HcINTLPTDDoneMap to check the PTDs that have completed their transactions. 7 INTL_IRQ 0 -- no event 1 -- The HC has detected the last PTD, and there is at least one interrupt transaction that has received ACK from the device. The microprocessor is required to read HcINTLPTDDoneMap to check the PTDs that have received ACK from the device. 6 ClkReady 0 -- no event 1 -- The HC has awakened from the `suspend' state, and its internal clock has turned on again. 5 HC 0 -- no event Suspended 1 -- The HC has been suspended and no USB activities are sent from the microprocessor for each ms. The microprocessor can suspend the HC by setting bits 6 and 7 of the HcControl register to logic 1. Once the HC is suspended, no SOF needs to be sent to the devices connected to downstream ports. OPR_Reg 0 -- no event 1 -- An HC operation has caused a hardware interrupt. It is necessary for the HCD to read the HcInterruptStatus register to determine the cause of the interrupt. 4 3 AllEOT Interrupt 0 -- no event 1 -- Data transfer has been completed by using the PIO transfer or the DMA transfer. This bit is set either when the value of the HcTransferCounter register has reached zero, or the EOT pin of the HC is triggered by an external signal. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 96 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcPInterrupt register: bit description...continued Symbol ISTL_1_ INT Description 0 -- no event 1 -- The transaction of the last PTD stored on the ISTL1 buffer has been completed. The microprocessor is required to read data from the ISTL1 buffer. The HCD must first read the HcBufferStatus register to check the status of the ISTL1 buffer before reading data to the microprocessor. 0 -- no event 1 -- The transaction of the last PTD stored on the ISTL0 buffer has been completed. The microprocessor is required to read data from the ISTL0 buffer. The HCD must first read the HcBufferStatus register to check the status of the ISTL0 buffer before reading data to the microprocessor. 0 -- no event 1 -- The HC is in the SOF state and it indicates the start of a new frame. The HCD must first read the HcBufferStatus register to check the status of the ISTL buffer before reading data to the microprocessor. For the microprocessor to perform the DMA transfer of ISO data from or to the ISTL buffer, the HC must first initialize the HcDMAConfiguration register. Table 69: Bit 2 1 ISTL_0_ INT 0 SOF_INT 15.4.5 HcPInterruptEnable register (R/W: 25H/A5H) The bits 9:0 in this register are the same as those in the HcPInterrupt register. The bits in this register are used together with bit 0 of the HcHardwareConfiguration register to enable or disable the bits in the HcPInterrupt register. At power-on, all the bits in this register are masked with logic 0. This means no interrupt request output on the interrupt pin INT1 can be generated. When a bit is set to logic 1, the interrupt for that bit is enabled. The bit allocation of the register is given in Table 70. Code (Hex): 25 -- read Code (Hex): A5 -- write Table 70: Bit Symbol HcPInterruptEnable register: bit allocation 15 14 13 reserved 12 11 10 9 OTG_IRQ_ Interrupt Enable 4 OPR Interrupt Enable 0 R/W 3 EOT Interrupt Enable 0 R/W 2 ISTL_1 Interrupt Enable 0 R/W 0 R/W 1 ISTL_0 Interrupt Enable 0 R/W 8 ATL_IRQ_ Interrupt Enable 0 R/W 0 SOF Interrupt Enable 0 R/W Reset Access Bit Symbol 7 INTL_IRQ_ Interrupt Enable 0 R/W 6 ClkReady 5 HC Suspended Enable 0 R/W Reset Access 0 R/W 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 97 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcPInterruptEnable register: bit description Symbol OTG_IRQ_ InterruptEnable ATL_IRQ_ InterruptEnable INTL_IRQ_ InterruptEnable ClkReady HCSuspendedEnable OPRInterruptEnable EOTInterruptEnable ISTL_1Interrupt Enable ISTL_0Interrupt Enable SOFInterrupt Enable Description reserved 0 -- power-up value 1 -- enables the OTG_IRQ interrupt 0 -- power-up value 1 -- enables the ATL_IRQ interrupt 0 -- power-up value 1 -- enables the INT_IRQ interrupt 0 -- power-up value 1 -- enables the ClkReady interrupt 0 -- power-up value 1 -- enables the HC suspended interrupt 0 -- power-up value 1 -- enables the 32-bit operational register's interrupt 0 -- power-up value 1 -- enables the EOT interrupt 0 -- power-up value 1 -- enables the ISTL_1 interrupt 0 -- power-up value 1 -- enables the ISTL_0 interrupt 0 -- power-up value 1 -- enables the SOF interrupt Table 71: Bit 15 to 10 9 8 7 6 5 4 3 2 1 0 15.5 HC miscellaneous registers 15.5.1 HcChipID register (R: 27H) This register contains the ID of the ISP1362. The upper byte identifies the product name (here 36H stands for the ISP1362). The lower byte indicates the revision number of the product including engineering samples. Table 72 contains the bit description of the register. Code (Hex): 27 -- read only Table 72: Bit 15 to 0 HcChipID register: bit description Symbol Access Value 3630H Description Chip ID of the ISP1362. CHIPID[15:0] R 15.5.2 HcScratch register (R/W: 28H/A8H) This register is for the HCD to save and restore values when required. The bit description is given in Table 73. Code (Hex): 28 -- read Code (Hex): A8 -- write 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 98 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcScratch register: bit description Symbol Access Value 0000H Description Scratch register value. Scratch[15:0] R/W Table 73: Bit 15 to 0 15.5.3 HcSoftwareReset register (W: A9H) This register provides a means for software reset of the HC. To reset the HC, the HCD must write a reset value of F6H to this register. On receiving this reset value, the HC resets all the HC and OTG registers, except its buffer memory. Table 74 contains the bit description of the register. Code (Hex): A9 -- write only Table 74: Bit 15 to 0 HcSoftwareReset register: bit description Symbol ResetValue [15:0] Access W Value 0000H Description Writing a reset value of F6H causes the HC to reset all the registers except its buffer memory. 15.6 HC buffer RAM control registers 15.6.1 HcBufferStatus register (R/W: 2CH/ACH) The bit allocation of the HcBufferStatus register is given in Table 75. Code (Hex): 2C -- read Code (Hex): AC -- write Table 75: Bit Symbol Reset Access Bit Symbol 7 reserved 6 ISTL1_ Active Status 0 R Table 76: Bit 15 to 11 10 9 8 HcBufferStatus register: bit allocation 15 14 13 reserved 5 ISTL0_ Active Status 0 R 4 Reset_HW PingPong Reg 0 R/W 3 ATL_Active 12 11 10 PairedPTD PingPong 0 R 2 INTL_ Active 0 R/W 9 ISTL1 BufferDone 0 R 1 ISTL1 BufferFull 0 R/W 8 ISTL0 BufferDone 0 R 0 ISTL0 BufferFull 0 R/W Reset Access - 0 R/W HcBufferStatus register: bit description Symbol PairedPTDPingPong ISTL1 BufferDone ISTL0 BufferDone Description reserved 0 -- Ping of paired PTD in ATL is active. 1 -- Pong of paired PTD in ATL is active. 0 -- The ISTL1 buffer has not yet been read by the HC. 1 -- The ISTL1 buffer has been read by the HC. 0 -- The ISTL0 buffer has not yet been read by the HC. 1 -- The ISTL0 buffer has been read by the HC. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 Product data Rev. 03 -- 06 January 2004 99 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcBufferStatus register: bit description...continued Symbol ISTL1_ActiveStatus ISTL0_ActiveStatus Reset_HW PingPong Reg ATL_Active INTL_Active ISTL1BufferFull ISTL0BufferFull Description reserved 0 -- The ISTL1 buffer is not accessed by the slave host. 1 -- The ISTL1 buffer is accessed by the slave host. 0 -- The ISTL0 buffer is not accessed by the slave host. 1 -- The ISTL0 buffer is accessed by the slave host. 0 to 1 -- resets internal hardware ping pong register to 0 when ATL_Active is 0. The hardware ping pong register can be read from bit 10 of this register. 1 to 0 -- has no effect. 0 -- The HC does not process the ATL buffer. 1 -- The HC processes the ATL buffer. 0 -- The HC does not process the INTL buffer. 1 -- The HC processes the INTL buffer. 0 -- The HC does not process the ISTL1 buffer. 1 -- The HC processes the ISTL1 buffer. 0 -- The HC does not process the ISTL0 buffer. 1 -- The HC processes the ISTL0 buffer. Table 76: Bit 7 6 5 4 3 2 1 0 15.6.2 HcDirectAddressLength register (R/W: 32H/B2H) The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL or ATL buffers. This register specifies the starting address of the buffer and byte count of the data to be addressed. Therefore, it allows the programmer to randomly access the buffer. The bit allocation of the register is given in Table 77. Code (Hex): 32 -- read Code (Hex): B2 -- write Table 77: Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access HcDirectAddressLength register: bit allocation 31 0 R/W 23 0 R/W 15 reserved 0 0 R/W 0 R/W 0 R/W 30 0 R/W 22 0 R/W 14 29 0 R/W 21 0 R/W 13 28 0 R/W 20 0 R/W 12 27 0 R/W 19 0 R/W 11 BufferStartAddress[14:8] 0 R/W 0 R/W 0 R/W 0 R/W 26 0 R/W 18 0 R/W 10 25 0 R/W 17 0 R/W 9 24 0 R/W 16 0 R/W 8 DataByteCount[15:8] DataByteCount[7:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 100 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 5 0 R/W 4 0 R/W 3 0 R/W 2 0 R/W 1 0 R/W 0 0 R/W Bit Symbol Reset Access 7 0 R/W 6 0 R/W Table 78: Bit 31 to 16 15 14 to 0 BufferStartAddress[7:0] HcDirectAddressLength register: bit description Symbol DataByteCount [15:0] Description Total number of bytes to be accessed. reserved BufferStartAddress[14:0] The starting address of the buffer for accessing of data. 15.6.3 HcDirectAddressData register (R/W: 45H/C5H) This is a data port for the HCD to access the ISTL, INTL or ATL buffers under the direct addressing mode. Table 79 contains the bit description of the register. Code (Hex): 45 -- read Code (Hex): C5 -- write Table 79: Bit 15 to 0 HcDirectAddressData register: bit description Symbol Access Value Description DataWord R/W [15:0] 0000H The data port for accessing the ISTL, INTL or ATL buffers. The address of the buffer and byte count of the data must be specified in the HcDirectAddressLength register. 15.7 Isochronous (ISO) transfer registers 15.7.1 HcISTLBufferSize register (R/W: 30H/B0H) This register requires you to allocate the size of the buffer to be used for ISO transactions. The buffer size specified in the register is applied to the ISTL0 and ISTL1 buffers. Therefore, ISTL0 and ISTL1 always have the same buffer size. Table 80 shows the bit description of the register. Code (Hex): 30 -- read Code (Hex): B0 -- write Table 80: Bit 15 to 0 HcISTLBufferSize register: bit description Symbol Access Value 0000H Description The size of the buffer to be used for ISO transactions and must be specified in bytes. ISTLBuffer R/W Size[15:0] 15.7.2 HcISTL0BufferPort register (R/W: 40H/C0H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ISTL0 buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL0 buffer is not allowed. The bit description of the register is given in Table 81. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 101 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Code (Hex): 40 -- read Code (Hex): C0 -- write Table 81: Bit HcISTL0BufferPort register: bit description Access Value 0000H Description The data in the ISTL0 buffer to be accessed through this data port. Symbol 15 to 0 DataWord R/W [15:0] The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD then sends the command (40H for reading from the ISTL0 buffer, and C0H for writing to the ISTL0 buffer) to the HC through the I/O port of the microprocessor. After the command is sent, the HCD starts reading data from the ISTL0 buffer or writing data to the ISTL0 buffer. While the HCD is accessing the buffer, the buffer pointer of ISTL0 also increases automatically. When the pointer has reached the initialized byte count of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the HcPInterrupt register to logic 1 and updates the HcBufferStatus register. 15.7.3 HcISTL1BufferPort register (R/W: 42H/C2H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ISTL1 buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ISTL1 buffer is not allowed. The bit description of the register is given in Table 82. Code (Hex): 42 -- read Code (Hex): C2 -- write Table 82: Bit HcISTL1BufferPort register: bit description Access Value 0000H Description The data in the ISTL1 buffer to be accessed through this data port. Symbol 15 to 0 DataWord R/W [15:0] The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD then sends the command (42H for reading from the ISTL1 buffer, and C2H for writing to the ISTL1 buffer) to the HC through the I/O port of the microprocessor. After the command is sent, the HCD starts reading data from the ISTL1 buffer or writing data to the ISTL1 buffer. While the HCD is accessing the buffer, the buffer pointer of ISTL1 also increases automatically. When the pointer has reached the initialized byte count of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit in the HcPInterrupt register to logic 1 and updates the HcBufferStatus register. 15.7.4 HcISTLToggleRate register (R/W: 47H/C7H) The rate of toggling between ISTL0 and ISTL1 is programmable. The HcISTLToggleRate register is provided for programming the required toggle rate in the range of 0 ms to 15 ms at intervals of 1 ms. The bit allocation of the register is shown in Table 83. Code (Hex): 47 -- read Code (Hex): C7 -- write 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 102 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 83: Bit Symbol Reset Access Bit Symbol Reset Access HcISTLToggleRate register: bit allocation 15 7 14 6 reserved Table 84: Bit 15 to 4 3 to 0 0 R/W 13 5 12 reserved 4 3 2 0 R/W 1 0 R/W 0 0 R/W 11 10 9 8 ISTLToggleRate[3:0] HcISTLToggleRate register: bit description Symbol ISTLToggleRate[3:0] Description reserved The required toggle rate in ms. 15.8 Interrupt transfer registers 15.8.1 HcINTLBufferSize register (R/W: 33H/B3H) This register allows you to allocate the size of the INTL buffer to be used for interrupt transactions. The default value of the buffer size is set to 128 bytes, and the maximum allowable allocated size is 4096 bytes. Table 85 shows the bit description of the register. Code (Hex): 33 -- read Code (Hex): B3 -- write Table 85: Bit HcINTLBufferSize register: bit description Access Value R/W 0080H Description The size of the buffer to be used for interrupt transactions and must be specified in bytes. Symbol 15 to 0 INTLBuffer Size[15:0] 15.8.2 HcINTLBufferPort register (R/W: 43H/C3H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the INTL buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the INTL buffer is not allowed. The bit description of the HcINTLBufferPort register is given in Table 86. Code (Hex): 43 -- read Code (Hex): C3 -- write Table 86: Bit HcINTLBufferPort register: bit description Access Value 0000H Description The data in the INTL buffer to be accessed through this data port. Symbol 15 to 0 DataWord R/W [15:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 103 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD then sends the command (43H for reading of the INTL buffer, and C3H for writing to the INTL buffer) to the HC through the I/O port of the microprocessor. After the command is sent, the HCD starts reading data from the INTL buffer or writing data to the INTL buffer. While the HCD is accessing the buffer, the buffer pointer of INTL also increases automatically. When the pointer has reached the initialized byte count of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the HcPInterrupt register to logic 1 and updates the HcBufferStatus register. 15.8.3 HcINTLBlkSize register (R/W: 53H/D3H) The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so that the HC can skip the current PTD and proceed to process the next PTD easily. The block size of the INTL buffer is required to be specified in this register and must be a multiple of 8 bytes. The default value of the block size is 64 bytes, and the maximum allowable block size is 1024 bytes. Table 87 shows the bit allocation of the register. Code (Hex): 53 -- read Code (Hex): D3 -- write Table 87: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W Table 88: Bit 15 to 10 9 to 0 0 R/W 7 6 5 HcINTLBlkSize register: bit allocation 15 14 13 reserved 4 0 R/W 3 0 R/W 2 0 R/W 12 11 10 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W BlockSize[9:8] BlockSize[7:0] HcINTLBlkSize register: bit description Symbol BlockSize[9:0] Description reserved The block size of the INTL buffer. 15.8.4 HcINTLPTDDoneMap register (R: 17H) This is a 32-bit register, and the bit description is given in Table 89. Every bit of the register represents the processing status of a PTD. Bit 0 of the register represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so on. The register is updated once every ms by the HC and is cleared upon read by the HCD. Bits that are set representing its corresponding PTDs are processed by the HC and the ACK token is received from the device. Code (Hex): 17 -- read only 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 104 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcINTLPTDDoneMap register: bit description Access Value 0000H Description 0 -- The PTD stored in the INTL buffer has not been successfully processed by the HC. 1 -- The PTD stored in the INTL buffer has been successfully processed by the HC. Table 89: Bit Symbol 31 to 0 PTDDone R Bits[31:0] 15.8.5 HcINTLPTDSkipMap register (R/W: 18H/98H) This is a 32-bit register, and the bit description is given in Table 90. Bit 0 of the register represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so on. When a bit is set by the HCD, the corresponding PTD is skipped and is not processed by the HC. The HC processes the skipped PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the block will cause unpredictable behavior of the HC. Code (Hex): 18 -- read Code (Hex): 98 -- write Table 90: Bit HcINTLPTDSkipMap register: bit description Access Value R/W 0000H Description 0 -- The HC processes the PTD. 1 -- The HC skips processing the PTD. Symbol 31 to 0 SkipBits [31:0] 15.8.6 HcINTLLastPTD register (R/W: 19H/99H) This is a 32-bit register, and Table 91 shows its bit description. Bit 0 of the register represents the first PTD stored in the INTL buffer, bit 1 represents the second PTD stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to the HC that its corresponding PTD is the last PTD stored in the INTL buffer. When the processing of the last PTD is complete, the HC proceeds to process ATL transactions. Code (Hex): 19 -- read Code (Hex): 99 -- write Table 91: Bit HcINTLLastPTD register: bit description Acc ess R/W Value 0000H Description 0 -- The PTD is not the last PTD stored in the buffer. 1 -- The PTD is the last PTD stored in the buffer. Symbol 31 to 0 LastPTD Bits[31:0] 15.8.7 HcINTLCurrentActivePTD register (R: 1AH) This register indicates which PTD stored in the INTL buffer is currently active and is updated by the HC. The HCD can use it as a buffer pointer to decide which PTD locations are currently free for filling in new PTDs to the buffer. This indication is to prevent the HCD from accidentally writing into the currently active PTD buffer location. Table 92 shows the bit allocation of the register. Code (Hex): 1A -- read only 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 105 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 92: Bit Symbol Reset Access Bit Symbol Reset Access HcINTLCurrentActivePTD register: bit allocation 15 7 14 6 reserved Table 93: Bit 15 to 5 4 to 0 0 R 0 R 13 5 12 reserved 4 3 2 ActivePTD[4:0] 0 R 0 R 0 R 1 0 11 10 9 8 HcINTLCurrentActivePTD register: bit description Symbol ActivePTD[4:0] Description reserved This 5-bit number represents the PTD that is currently active. 15.9 Control and bulk transfer (aperiodic transfer) registers 15.9.1 HcATLBufferSize register (R/W: 34H/B4H) This register allows you to allocate the size of the ATL buffer to be used for aperiodic transactions. The default value of the buffer size is set to 512 bytes, and the maximum allowable allocated size is 4096 bytes. The bit description of the register is given in Table 94. Code (Hex): 34 -- read Code (Hex): B4 -- write Table 94: Bit HcATLBufferSize register: bit description Access Value R/W 0200H Description The size of the buffer to be used for aperiodic transactions and must be specified in bytes. Symbol 15 to 0 ATLBuffer Size[15:0] 15.9.2 HcATLBufferPort register (R/W: 44H/C4H) In addition to the HcDirectAddressData register, the ISP1362 provides this register to act as another data port for accessing the ATL buffer. The starting address for accessing the buffer is always fixed at 0000H. Therefore, random access of the ATL buffer is not allowed. The bit description of the HcATLBufferPort register is given in Table 95. Code (Hex): 44 -- read Code (Hex): C4 -- write Table 95: Bit HcATLBufferPort register: bit description Access R/W Value 0000H Description The data of the ATL buffer to be accessed through this data port. Symbol 15 to 0 DataWord [15:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 106 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD then sends the command (44H for reading from the ATL buffer, and C4H for writing to the ATL buffer) to the HC through the I/O port of the microprocessor. After the command is sent, the HCD starts reading data from the ATL buffer or writing data to the ATL buffer. While the HCD is accessing the buffer, the buffer pointer of ATL also increases automatically. When the pointer has reached the initialized byte count of the HcTransferCounter register, the HC sets the AllEOTInterrupt bit of the HcPInterrupt register to logic 1 and updates the HcBufferStatus register. 15.9.3 HcATLBlkSize register (R/W: 54H/D4H) The ISP1362 partitions the ATL buffer into several equal sized blocks so that the HC can skip the current PTD and proceed to process the next PTD easily. The block size of the ATL buffer must be specified in this register and must be a multiple of 8 bytes. The bit allocation of the HcATLBlkSize register is given in Table 96. Code (Hex): 54 -- read Code (Hex): D4 -- write Table 96: Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W Table 97: Bit 15 to 10 9 to 0 0 R/W 7 6 5 HcATLBlkSize register: bit allocation 15 14 13 reserved 4 0 R/W 3 0 R/W 2 0 R/W 12 11 10 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W BlockSize[9:8] BlockSize[7:0] HcATLBlkSize register: bit description Symbol Description reserved BlockSize[9:0] The block size of the ATL buffer. 15.9.4 HcATLPTDDoneMap register (R: 1BH) This is a 32-bit register. The bit description of the register is given in Table 98. Every bit of the register represents the processing status of a PTD. Bit 0 of the register represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer, and so on. The register is immediately updated after the completion of each ATL PTD processing. It is cleared upon reading by the HCD. Bits that are set representing its corresponding PTDs have been processed by the HC and ACK token has been received from the device. Code (Hex): 1B -- read only 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 107 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller HcATLPTDDoneMap register: bit description Symbol PTDDone Bits[31:0] Access Value R 0000H Description 0 -- The PTD stored in the ATL buffer was not successfully processed by the HC. 1 -- The PTD stored in the ATL buffer was successfully processed by the HC. Table 98: Bit 31 to 0 15.9.5 HcATLPTDSkipMap register (R/W: 1CH/9CH) This is a 32-bit register, and the bit description is given in Table 99. Bit 0 of the register represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer, and so on. When the bit is set by the HCD, the corresponding PTD is skipped and is not processed by the HC. The HC processes the skipped PTD only if the HCD has reset its corresponding skipped bit to logic 0. Clearing the corresponding bit in the HcATLPTDSkipMap register when there is no valid data in the block will cause unpredictable behavior of the HC. Code (Hex): 1C -- read Code (Hex): 9C -- write Table 99: Bit HcATLPTDSkipMap register: bit description Access Value R/W 0000H Description 0 -- The HC processes the PTD. 1 -- The HC skips processing the PTD. Symbol 31 to 0 SkipBits [31:0] 15.9.6 HcATLLastPTD register (R/W: 1DH/9DH) This is a 32-bit register. Table 100 gives the bit description of the register. Bit 0 of the register represents the first PTD stored in the ATL buffer, bit 1 represents the second PTD stored in the buffer, and so on. The bit that is set to logic 1 by the HCD is used as an indication to the HC that its corresponding PTD is the last PTD stored in the ATL buffer. When the processing of the last PTD is complete, the HC loops back to process the first PTD stored in the buffer. Code (Hex): 1D -- read Code (Hex): 9D -- write Table 100: HcATLLastPTD register: bit description Bit 31 to 0 Symbol LastPTD Bits[31:0] Access Value R/W Description 0000H 0 -- The PTD is not the last PTD stored in the buffer. 1 -- The PTD is the last PTD stored in the buffer. 15.9.7 HcATLCurrentActivePTD register (R: 1EH) This register indicates which PTD stored in the ATL buffer is currently active and is updated by the HC. The HCD can use it as a buffer pointer to decide which PTD locations are currently free for filling in new PTDs to the buffer. This indication helps to prevent the HCD from accidentally writing into the currently active PTD buffer location. Table 101 shows the bit allocation of the register. Code (Hex): 1E -- read only 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 108 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 101: HcATLCurrentActivePTD register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 7 6 reserved 0 R 0 R 5 4 15 14 13 12 reserved 3 2 ActivePTD[4:0] 0 R 0 R 0 R 1 0 11 10 9 8 Table 102: HcATLCurrentActivePTD register: bit description Bit 15 to 5 4 to 0 Symbol Description reserved ActivePTD[4:0] This 5-bit number represents the PTD that is currently active. 15.9.8 HcATLPTDDoneThresholdCount register (R/W: 51H/D1H) This register specifies the number of ATL PTD done required to trigger an ATL PTDDoneCount. If set to 0x08, the HC would trigger the ATL interrupt (in the HcPInterrupt register) once for every 8 ATL PTD done. Table 103 shows the bit allocation of the register. Remark: Do not write 0x0000 to this register. Code (Hex): 51 -- read Code (Hex): D1 -- write Table 103: HcATLPTDDoneThresholdCount register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 7 6 reserved 0 R/W 0 R/W 5 4 15 14 13 12 reserved 3 2 PTDDoneCount[4:0] 0 R/W 0 R/W 1 R/W 1 0 11 10 9 8 Table 104: HcATLPTDDoneThresholdCount register: bit description Bit 15 to 5 4 to 0 Symbol PTDDoneCount[4:0] Description reserved Number of PTDs processed by the HC. 15.9.9 HcATLPTDDoneThresholdTimeOut register (R/W: 52H/D2H) This register indicates the number of ms from the last time when the ATL interrupt (in the HcPInterrupt register) was set, of which, if the number of ATL PTDDone is still less than HcATLPTDDoneThresholdCount, the HC would trigger an ATL interrupt (in 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 109 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller the HcPInterrupt register) to indicate a time-out situation, provided HcATLPTDDoneMap is currently 0x0000 0000. Table 105 shows the bit allocation of the HcATLPTDDone register. Remark: If the time-out indication is not required by software, or there is no active PTD in the ATL buffer, write 0x0000 to this register. Code (Hex): 52 -- read Code (Hex): D2 -- write Table 105: HcATLPTDDoneThresholdTimeOut register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 7 6 5 4 0 R/W 15 14 13 12 reserved 3 0 R/W 2 0 R/W 1 0 R/W 0 1 R/W 11 10 9 8 PTDDoneTimeOut[7:0] Table 106: HcATLPTDDoneThresholdTimeOut register: bit description Bit 15 to 8 7 to 0 Symbol PTDDoneTimeOut[7:0] Description reserved Maximum allowable time in ms for the HC to retry a transaction with NAK returned. 16. Device Controller (DC) registers The functions and registers of the DC are accessed using commands, which consist of a command code followed by optional data bytes (read or write action). An overview of the available commands and registers is given in Table 107. A complete access consists of two phases: 1. Command phase: when address pin A0 = HIGH, the DC interprets the data on the lower byte of the bus (bits D7 to D0) as a command code. Commands without a data phase are immediately executed. 2. Data phase (optional): when address pin A0 = LOW, the DC transfers the data on the bus to or from a register or endpoint buffer memory. In case of multi-byte registers, the least significant byte or word are accessed first. The following applies to a register or buffer memory access in the 16-bit bus mode: * The upper byte (bits D15 to D8) in the command phase or the undefined byte in the data phase are ignored. * The access of registers is word-aligned: byte access is not allowed. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 110 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller * If the packet length is odd, the upper byte of the last word in an IN endpoint buffer is not transmitted to the host. When reading from an OUT endpoint buffer, the upper byte of the last word must be ignored by the firmware. The packet length is stored in the first two bytes of the endpoint buffer. Table 107: DC command and register summary Name Initialization commands Write Control OUT Configuration Write Control IN Configuration Write Endpoint n Configuration (n = 1 to 14) Read Control OUT Configuration Read Control IN Configuration Read Endpoint n Configuration (n = 1 to 14) Write or read Device Address Write or read Mode register Write or read Hardware Configuration Write or read DcInterruptEnable register Write or read DMA Configuration Write or read DMA Counter Reset Device Data flow commands Write Control OUT Buffer Write Control IN Buffer Write Endpoint n Buffer (n = 1 to 14) Read Control OUT Buffer Read Control IN Buffer Read Endpoint n Buffer (n = 1 to 14) Stall Control OUT Endpoint Stall Control IN Endpoint Stall Endpoint n (n = 1 to 14) Read Control OUT Status Read Control IN Status illegal: endpoint is read-only buffer memory endpoint 0 IN buffer memory endpoint 1 to 14 (IN endpoints only) buffer memory endpoint 0 OUT illegal: endpoint is write-only buffer memory endpoint 1 to 14 (OUT endpoints only) Endpoint 0 OUT Endpoint 0 IN Endpoint 1 to 14 DcEndpointStatus register endpoint 0 OUT DcEndpointStatus register endpoint 0 IN (00) 01 02 to 0F N 64 bytes isochronous: N 1023 bytes interrupt/bulk: N 64 bytes 10 (11) 12 to 1F N 64 bytes isochronous: N 1023 bytes[4] interrupt/bulk: N 64 bytes 40 41 42 to 4F 50 51 read 1 byte[2] read 1 byte[2] DcEndpointConfiguration register endpoint 0 OUT DcEndpointConfiguration register endpoint 0 IN DcEndpointConfiguration register endpoint 1 to 14 DcEndpointConfiguration register endpoint 0 OUT DcEndpointConfiguration register endpoint 0 IN DcEndpointConfiguration register endpoint 1 to 14 DcAddress register DcMode register DcInterruptEnable register DcDMAConfiguration register DcDMACounter register resets all registers 20 21 22 to 2F 30 31 32 to 3F B6/B7 B8/B9 C2/C3 F0/F1 F2/F3 F6 write 1 byte[2] write 1 byte[2] write 1 byte[2] read 1 byte[2] read 1 byte[2] read 1 byte[2] write or read 1 byte[2] write or read 1 byte[2] write or read 2 bytes write or read 4 bytes write or read 2 bytes write or read 2 bytes Destination Code (Hex) Transaction[1] DcHardwareConfiguration register BA/BB 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 111 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 107: DC command and register summary...continued Name Read Endpoint n Status (n = 1 to 14) Validate Control OUT Buffer Validate Control IN Buffer Validate Endpoint n Buffer (n = 1 to 14) Clear Control OUT Buffer Clear Control IN Buffer Clear Endpoint n Buffer (n = 1 to 14) Unstall Control OUT Endpoint Unstall Control IN Endpoint Unstall Endpoint n (n = 1 to 14) Check Control OUT Status[6] Check Control IN Status[6] Check Endpoint n Status (n = 1 to 14)[6] Acknowledge Set-up General commands Read Control OUT Error Code Read Control IN Error Code Read Endpoint n Error Code (n = 1 to 14) Unlock Device Write or read DcScratch register Read Frame Number Read Chip ID Read DcInterrupt register [1] [2] [3] [4] [5] [6] Destination DcEndpointStatus register n endpoint 1 to 14 illegal: IN endpoints only[3] buffer memory endpoint 0 IN[3] buffer memory endpoint 1 to 14 (IN endpoints only)[3] buffer memory endpoint 0 OUT illegal[5] buffer memory endpoint 1 to 14 (OUT endpoints only)[5] Endpoint 0 OUT Endpoint 0 IN Endpoint 1 to 14 DcEndpointStatusImage register endpoint 0 OUT DcEndpointStatusImage register endpoint 0 IN Code (Hex) 52 to 5F (60) 61 62 to 6F 70 (71) 72 to 7F 80 81 82 to 8F D0 D1 Transaction[1] read 1 byte[2] - read 1 byte[2] read 1 byte[2] read 1 byte[2] read 1 byte[2] read 1 byte[2] read 1 byte[2] write 2 bytes write or read 2 bytes read 1 or 2 bytes read 2 bytes read 4 bytes DcEndpointStatusImage register n D2 to DF endpoint 1 to 14 Endpoint 0 IN and OUT DcErrorCode register endpoint 0 OUT DcErrorCode register endpoint 0 IN DcErrorCode register endpoint 1 to 14 all registers with write access DcScratch register DcFrameNumber register DcChipID register DcInterrupt register F4 A0 A1 A2 to AF B0 B2/B3 B4 B5 C0 With N representing the number of bytes, the number of words for 16-bit bus width is: (N + 1) divided by 2. When accessing an 8-bit register in the 16-bit mode, the upper byte is invalid. Validating an OUT endpoint buffer causes unpredictable behavior of the DC. During the isochronous transfer in the 16-bit mode, because N 1023, the firmware must manage the upper byte. Clearing an IN endpoint buffer causes unpredictable behavior of the DC. Reads a copy of the Status register: executing this command does not clear any status bits or interrupt bits. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 112 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 16.1 Initialization commands Initialization commands are used during the enumeration process of the USB network. These commands are used to configure and enable the embedded endpoints. They also serve to set the USB assigned address of the DC and to perform a device reset. 16.1.1 DcEndpointConfiguration register (R/W: 30H-3FH/20H-2FH) This command is used to access the DcEndpointConfiguration register (ECR) of the target endpoint. It defines the endpoint type (isochronous or bulk/interrupt), direction (OUT/IN), buffer memory size and buffering scheme. It also enables the endpoint buffer memory. The register bit allocation is shown in Table 108. A bus reset will disable all endpoints. The allocation of buffer memory only takes place after all 16 endpoints have been configured in sequence (from endpoint 0 OUT to endpoint 14). Although the control endpoints have fixed configurations, they must be included in the initialization sequence and must be configured with their default values (see Table 14). Automatic buffer memory allocation starts when endpoint 14 has been configured. Remark: If any change is made to an endpoint configuration that affects the allocated memory (size, enable/disable), the buffer memory contents of all endpoints becomes invalid. Therefore, all valid data must be removed from enabled endpoints before changing the configuration. Code (Hex): 20 to 2F -- write (control OUT, control IN, endpoint 1 to 14) Code (Hex): 30 to 3F -- read (control OUT, control IN, endpoint 1 to 14) Transaction -- write or read 1 byte (code or data) Table 108: DcEndpointConfiguration register: bit allocation Bit Symbol Reset Access 7 FIFOEN 0 R/W 6 EPDIR 0 R/W 5 DBLBUF 0 R/W 4 FFOISO 0 R/W 0 R/W 0 R/W 3 2 FFOSZ[3:0] 0 R/W 0 R/W 1 0 Table 109: DcEndpointConfiguration register: bit description Bit 7 Symbol FIFOEN Description Logic 1 indicates an enabled buffer memory with allocated memory. Logic 0 indicates a disabled buffer memory (no bytes allocated). This bit defines the endpoint direction (0 = OUT, 1 = IN); it also determines the DMA transfer direction (0 = read, 1 = write). Logic 1 indicates that this endpoint has double buffering. Logic 1 indicates an isochronous endpoint. Logic 0 indicates a bulk or interrupt endpoint. Selects the buffer memory size according to Table 15. 6 5 4 3 to 0 EPDIR DBLBUF FFOISO FFOSZ[3:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 113 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 16.1.2 DcAddress register (R/W: B7H/B6H) This command is used to set the USB assigned address in the DcAddress register and enable the USB device. The DcAddress register bit allocation is shown in Table 110. A USB bus reset sets the device address to 00H (internally) and enables the device. The value of the DcAddress register (accessible by the microprocessor) is not altered by the bus reset. In response to the standard USB request Set Address, the firmware must issue a Write Device Address command, followed by sending an empty packet to the host. The new device address is activated when the host acknowledges the empty packet. Code (Hex): B6/B7 -- write or read DcAddress register Transaction -- write or read 1 byte (code or data) Table 110: DcAddress register: bit allocation Bit Symbol Reset Access 7 DEVEN 0 R/W 0 R/W 0 R/W 0 R/W 6 5 4 3 DEVADR[6:0] 0 R/W 0 R/W 0 R/W 0 R/W 2 1 0 Table 111: DcAddress register: bit description Bit 7 6 to 0 Symbol DEVEN DEVADR[6:0] Description Logic 1 enables the device. This field specifies the USB device address. 16.1.3 DcMode register (R/W: B9H/B8H) This command is used to access the DcMode register, which consists of 1 byte (bit allocation: see Table 112). In the 16-bit bus mode, the upper byte is ignored. The DcMode register controls the DMA bus width, the resume and suspend modes, interrupt activity, and SoftConnect operation. It can be used to enable the debug mode, in which all errors and Not Acknowledge (NAK) conditions will generate an interrupt. Code (Hex): B8/B9 -- write or read DcMode register Transaction -- write or read 1 byte (code or data) Table 112: DcMode register: bit allocation Bit Symbol Reset Access [1] 7 reserved 1[1] R/W 6 0 R/W 5 GOSUSP 0 R/W 4 reserved 0 R/W 3 INTENA 0[1] R/W 2 DBGMOD 0[1] R/W 1 reserved 0[1] R/W 0 SOFTCT 0[1] R/W Unchanged by a bus reset. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 114 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 113: DcMode register: bit description Bit 7 to 6 5 4 3 2 Symbol GOSUSP INTENA DBGMOD Description reserved Writing logic 1 followed by logic 0 will activate the `suspend' mode. reserved Logic 1 enables all interrupts. Bus reset value: unchanged. Logic 1 enables debug mode, in which all NAKs and errors will generate an interrupt. Logic 0 selects normal operation, in which interrupts are generated on every ACK (bulk endpoints) or after every data transfer (isochronous endpoints). Bus reset value: unchanged. reserved Logic 1 enables SoftConnect. This bit is ignored if EXTPUL = 1 in the DcHardwareConfiguration register (see Table 114). Bus reset value: unchanged. Remark: In the OTG mode, this bit is ignored. The LOC_CONN bit of the OtgControl register controls the pull-up resistor on the OTG_DP1 pin. 1 0 SOFTCT 16.1.4 DcHardwareConfiguration register (R/W: BBH/BAH) This command is used to access the DcHardwareConfiguration register, which consists of two bytes. The first (lower) byte contains the device configuration and control values, the second (upper) byte holds the clock control bits and the clock division factor. The bit allocation is given in Table 114. A bus reset will not change any of the programmed bit values. The DcHardwareConfiguration register controls the connection to the USB bus, clock activity and power supply during the `suspend' state, as well as output clock frequency, DMA operating mode and pin configurations (polarity, signalling mode). Code (Hex): BA/BB -- write or read DcHardwareConfiguration register Transaction -- write or read 2 bytes (code or data) Table 114: DcHardwareConfiguration register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 15 reserved 7 DAKOLY 0 R/W 14 EXTPUL 0 R/W 6 DRQPOL 1 R/W 13 NOLAZY 1 R/W 5 DAKPOL 0 R/W 12 CLKRUN 0 R/W 4 reserved 0 0 R/W 3 WKUPCS 0 R/W 0 R/W 2 reserved 1 R/W 11 10 CKDIV[3:0] 1 R/W 1 INTLVL 0 R/W 1 R/W 0 INTPOL 0 R/W 9 8 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 115 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 115: DcHardwareConfiguration register: bit description Bit 15 14 Symbol EXTPUL Description reserved Logic 1 indicates that an external 1.5 k pull-up resistor is used on pin OTG_DP1 (in the device mode) and that SoftConnect is not used. Bus reset value: unchanged. Logic 1 disables output on pin CLKOUT of the LazyClock frequency (115 kHz 50 %) during the `suspend' state. Logic 0 causes pin CLKOUT to switch to LazyClock output after approximately 2 ms delay, following the setting of bit GOSUSP of the DcMode register. Bus reset value: unchanged. Logic 1 indicates that the internal clocks are always running, even during the `suspend' state. Logic 0 switches off the internal oscillator and PLL, when they are not needed. During the `suspend' state, this bit must be made logic 0 to meet the suspend current requirements. The clock is stopped after a delay of approximately 2 ms, following the setting of bit GOSUSP of the DcMode register. Bus reset value: unchanged. This field specifies the clock division factor N, which controls the clock frequency on output CLKOUT. The output frequency in MHz is given by 48 ( N + 1 ) . The clock frequency range is 3 MHz to 48 MHz (N = 0 to 15), with a reset value of 12 MHz (N = 3). The hardware design guarantees no glitches during frequency change. Bus reset value: unchanged. Logic 1 selects the DACK-only DMA mode. Logic 0 selects the 8237 compatible DMA mode. Bus reset value: unchanged. Selects the DREQ2 pin signal polarity (0 = active LOW; 1 = active HIGH). Bus reset value: unchanged. Selects the DACK2 pin signal polarity (0 = active LOW; 1 = active HIGH). Bus reset value: unchanged. reserved Logic 1 enables remote wake-up using a LOW level on input CS. Bus reset value: unchanged. reserved Selects the interrupt signalling mode on output (0 = level; 1 = pulsed). In the pulsed mode, an interrupt produces 166 ns pulse. Bus reset value: unchanged. Selects the INT2 signal polarity (0 = active LOW; 1 = active HIGH). Bus reset value: unchanged. 13 NOLAZY 12 CLKRUN 11 to 8 CKDIV[3:0] 7 6 5 4 3 2 1 DAKOLY DRQPOL DAKPOL WKUPCS INTLVL 0 INTPOL 16.1.5 DcInterruptEnable register (R/W: C3H/C2H) This command is used to individually enable or disable interrupts from all endpoints, as well as interrupts caused by events on the USB bus (SOF, SOF lost, EOT, suspend, resume, reset). A bus reset will not change any of the programmed bit values. The command accesses the DcInterruptEnable register, which consists of 4 bytes. The bit allocation is given in Table 116. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 116 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Code (Hex): C2/C3 -- write or read InterruptEnable register Transaction -- write or read 4 bytes (code or data) Table 116: DcInterruptEnable register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 23 IEP14 0 R/W 15 IEP6 0 R/W 7 reserved 22 IEP13 0 R/W 14 IEP5 0 R/W 6 SP_IEEOT 0 R/W 21 IEP12 0 R/W 13 IEP4 0 R/W 5 IEPSOF 0 R/W 20 IEP11 0 R/W 12 IEP3 0 R/W 4 IESOF 0 R/W 31 30 29 28 reserved 19 IEP10 0 R/W 11 IEP2 0 R/W 3 IEEOT 0 R/W 18 IEP9 0 R/W 10 IEP1 0 R/W 2 IESUSP 0 R/W 17 IEP8 0 R/W 9 IEP0IN 0 R/W 1 IERESM 0 R/W 16 IEP7 0 R/W 8 IEP0OUT 0 R/W 0 IERST 0 R/W 27 26 25 24 Table 117: DcInterruptEnable register: bit description Bit 31 to 24 23 to 10 9 8 7 6 5 4 3 2 1 0 Symbol IEP0IN IEP0OUT SP_IEEOT IEPSOF IESOF IEEOT IESUSP IERESM IERST Description reserved; must write logic 0 Logic 1 enables interrupts from the control IN endpoint. Logic 1 enables interrupts from the control OUT endpoint. reserved Logic 1 enables interrupt upon detection of a short packet. Logic 1 enables 1 ms interrupts upon detection of Pseudo SOF. Logic 1 enables interrupt upon the SOF detection. Logic 1 enables interrupt upon the EOT detection. Logic 1 enables interrupt upon detection of a `suspend' state. Logic 1 enables interrupt upon detection of a `resume' state. Logic 1 enables interrupt upon detection of a bus reset. IEP14 to IEP1 Logic 1 enables interrupts from the indicated endpoint. 16.1.6 DcDMAConfiguration (R/W: F1H/F0H) This command defines the DMA configuration of the DC and enables or disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists of two bytes. The bit allocation is given in Table 118. A bus reset will clear bit DMAEN (DMA disabled), all other bits remain unchanged. Code (Hex): F0/F1 -- write or read DMA Configuration Transaction -- write or read 2 bytes (code or data) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 117 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 118: DcDMAConfiguration register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access [1] 15 CNTREN 0[1] R/W 7 0[1] R/W 14 SHORTP 0[1] R/W 6 EPDIX[3:0] 0[1] R/W 13 5 0[1] R/W 12 4 0[1] R/W 11 reserved 3 DMAEN 0 R/W 10 2 reserved - 9 1 0[1] R/W 8 0 0[1] R/W BURSTL[1:0] Unchanged by a bus reset. Table 119: DcDMAConfiguration register: bit description Bit 15 Symbol CNTREN Description Logic 1 enables the generation of an EOT condition, when the DcDMACounter register reaches zero. Bus reset value: unchanged. Logic 1 enables the short or empty packet mode. When receiving (OUT endpoint) a short or empty packet, an EOT condition is generated. When transmitting (IN endpoint), this bit should be cleared. Bus reset value: unchanged. reserved Indicates the destination endpoint for DMA, see Table 17. Writing logic 1 enables DMA transfer, logic 0 forces the end of an ongoing DMA transfer. Reading this bit indicates whether DMA is enabled (0 = DMA stopped; 1 = DMA enabled). This bit is cleared by a bus reset. reserved Selects the DMA burst length: 00 -- single-cycle mode (1 byte) 01 -- burst mode (4 bytes) 10 -- burst mode (8 bytes) 11 -- burst mode (16 bytes) Bus reset value: unchanged. 14 SHORTP 13 to 8 7 to 4 3 EPDIX[3:0] DMAEN 2 1 to 0 BURSTL[1:0] 16.1.7 DcDMACounter register (R/W: F3H/F2H) This command accesses the DcDMACounter register, which consists of two bytes. The bit allocation is given in Table 120. Writing to the register sets the number of bytes for a DMA transfer. Reading the register returns the number of remaining bytes in the current transfer. A bus reset will not change the programmed bit values. The internal DMA counter is automatically reloaded from the DcDMACounter register when DMA is re-enabled (DMAEN = 1). See Section 16.1.6 for more details. Code (Hex): F2/F3 -- write or read DcDMACounter register Transaction -- write or read 2 bytes (code or data) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 118 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 120: DcDMACounter register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 7 0 R/W 6 0 R/W 5 15 14 13 12 0 R/W 4 0 R/W 11 0 R/W 3 0 R/W 10 0 R/W 2 0 R/W 9 0 R/W 1 0 R/W 8 0 R/W 0 0 R/W DMACR[15:8] DMACR[7:0] Table 121: DcDMACounter register: bit description Bit 15 to 0 Symbol DMACR[15:0] Description DcDMACounter register 16.1.8 Reset Device (F6H) This command resets the DC in the same way as an external hardware reset by using the input RESET. All registers are initialized to their `reset' values. Code (Hex): F6 -- reset the device Transaction -- none (code only) 16.2 Data flow commands Data flow commands are used to manage the data transmission between the USB endpoints and the system microprocessor. Much of the data flow is initiated using an interrupt to the microprocessor. The data flow commands are used to access the endpoints and determine whether the endpoint buffer memory contains valid data. Remark: The IN buffer of an endpoint contains input data for the host. The OUT buffer receives output data from the host. 16.2.1 Write or read Endpoint Buffer (R/W: 10H,12H-1FH/01H-0FH) This command is used to access endpoint buffer memory for reading or writing. First, the buffer pointer is reset to the beginning of the buffer. Following the command, a maximum of (N + 2) bytes can be written or read, N representing the size of the endpoint buffer. For 16-bit access, the maximum number of words is (M + 1), with M given by (N + 1) divided by 2. After each read or write action, the buffer pointer is automatically incremented by two. In direct memory access (DMA), the first two bytes or the first word (the packet length) are skipped: transfers start at the third byte or the second word of the endpoint buffer. When reading, the DC can detect the last byte or word by using the EOP condition. When writing to a bulk or interrupt endpoint, the endpoint buffer must be completely filled before sending data to the host. Exception: when a DMA transfer is stopped by an external EOT condition, the current buffer content (full or not) is sent to the host. Remark: Reading data after a Write Endpoint Buffer command or writing data after a Read Endpoint Buffer command data will cause unpredictable behavior of the DC. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 119 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Code (Hex): 01 to 0F -- write (control IN, endpoint 1 to 14) Code (Hex): 10, 12 to 1F -- read (control OUT, endpoint 1 to 14) Transaction -- write or read maximum N + 2 bytes (isochronous endpoint: N 1023, bulk/interrupt endpoint: N 32) (code or data) The data in the endpoint buffer memory must be organized as shown in Table 122. An example of endpoint buffer memory access is given in Table 123. Table 122: Endpoint buffer memory organization Word # 0 (lower byte) 0 (upper byte) 1 (lower byte) 1 (upper byte) ... M = (N + 1)/2 Description packet length (lower byte) packet length (upper byte) data byte 1 data byte 2 ... data byte N Table 123: Example of endpoint buffer memory access A0 HIGH LOW LOW LOW ... Phase command data data data ... Bus lines D[7:0] D[15:8] D[15:0] D[15:0] D[15:0] ... Word # 0 1 2 ... Description command code (00H to 1FH) ignored packet length data word 1 (data byte 2, data byte 1) data word 2 (data byte 4, data byte 3) ... Remark: There is no protection against writing or reading past a buffer's boundary, against writing into an OUT buffer or reading from an IN buffer. Any of these actions could cause an incorrect operation. Data residing in an OUT buffer is only meaningful after a successful transaction. Exception: during DMA access of a double-buffered endpoint, the buffer pointer automatically points to the secondary buffer after reaching the end of the primary buffer. 16.2.2 Read Endpoint Status (R: 50H-5FH) This command is used to read the status of an endpoint buffer memory. The command accesses the DcEndpointStatus register, the bit allocation of which is shown in Table 124. Reading the DcEndpointStatus register will clear the interrupt bit set for the corresponding endpoint in the DcInterrupt register (see Table 140). All bits of the DcEndpointStatus register are read-only. Bit EPSTAL is controlled by the Stall or Unstall commands and by the reception of a SET-UP token (see Section 16.2.3). Code (Hex): 50 to 5F -- read (control OUT, control IN, endpoint 1 to 14) Transaction -- read 1 byte (code only) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 120 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 124: DcEndpointStatus register: bit allocation Bit Symbol Reset Access 7 EPSTAL 0 R 6 EPFULL1 0 R 5 EPFULL0 0 R 4 DATA_PID 0 R 3 OVER WRITE 0 R 2 SETUPT 0 R 1 CPUBUF 0 R 0 reserved - Table 125: DcEndpointStatus register: bit description Bit 7 Symbol EPSTAL Description This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not stalled). Set to logic 1 by a Stall Endpoint command, cleared to logic 0 by an Unstall Endpoint command. The endpoint is automatically unstalled on receiving a SET-UP token. 6 5 4 3 EPFULL1 EPFULL0 DATA_PID OVERWRITE Logic 1 indicates that the secondary endpoint buffer is full. Logic 1 indicates that the primary endpoint buffer is full. This bit indicates the data PID of the next packet (0 = DATA PID; 1 = DATA1 PID). This bit is set by hardware. Logic 1 indicates that a new Set-up packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. This bit is cleared by reading, if writing the set-up data has finished. Firmware must check this bit before sending an Acknowledge Set-up command or stalling the endpoint. Upon reading logic 1, the firmware must stop ongoing set-up actions and wait for a new Set-up packet. 2 1 0 SETUPT CPUBUF Logic 1 indicates that the buffer contains a Set-up packet. This bit indicates which buffer is currently selected for CPU access (0 = primary buffer; 1 = secondary buffer). reserved 16.2.3 Stall Endpoint or Unstall Endpoint (40H-4FH/80H-8FH) These commands are used to stall or unstall an endpoint. The commands modify the content of the DcEndpointStatus register (see Table 124). A stalled control endpoint is automatically unstalled when it receives a SET-UP token, regardless of the packet content. If the endpoint should stay in its stalled state, the microprocessor can re-stall it with the Stall Endpoint command. When a stalled endpoint is unstalled (either by using the Unstall Endpoint command or by receiving a SET-UP token), it is also re-initialized. This flushes the buffer: if it is an OUT buffer, it waits for a DATA 0 PID; if it is an IN buffer, it writes a DATA 0 PID. Code (Hex): 40 to 4F -- stall (control OUT, control IN, endpoint 1 to 14) Code (Hex): 80 to 8F -- unstall (control OUT, control IN, endpoint 1 to 14) Transaction -- none (code only) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 121 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 16.2.4 Validate Endpoint Buffer (61H-6FH) This command signals the presence of valid data for transmission to the USB host, by setting the Buffer Full flag of the selected IN endpoint. This indicates that the data in the buffer is valid and can be sent to the host, when the next IN token is received. For a double-buffered endpoint, this command switches the current buffer memory for CPU access. Remark: For special aspects of the control IN endpoint, see Section 13.3.6. Code (Hex): 61 to 6F -- validate endpoint buffer (control IN, endpoint 1 to 14) Transaction -- none (code only) 16.2.5 Clear Endpoint Buffer (70H, 72H-7FH) This command unlocks and clears the buffer of the selected OUT endpoint, allowing the reception of new packets. Reception of a complete packet causes the Buffer Full flag of an OUT endpoint to be set. Any subsequent packets are refused by returning a NAK condition, until the buffer is unlocked using this command. For a double-buffered endpoint, this command switches the current buffer memory for CPU access. Remark: For special aspects of the control OUT endpoint, see Section 13.3.6. Code (Hex): 70, 72 to 7F -- clear endpoint buffer (control OUT, endpoint 1 to 14) Transaction -- none (code only) 16.2.6 DcEndpointStatusImage register (D0H-DFH) This command is used to check the status of the selected endpoint buffer memory without clearing any status or interrupt bits. The command accesses the DcEndpointStatusImage register, which contains a copy of the DcEndpointStatus register. The bit allocation of the DcEndpointStatusImage register is shown in Table 126. Code (Hex): D0 to DF -- check status (control OUT, control IN, endpoint 1 to 14) Transaction -- write or read 1 byte (code or data) Table 126: DcEndpointStatusImage register: bit allocation Bit Symbol Reset Access 7 EPSTAL 0 R 6 EPFULL1 0 R 5 EPFULL0 0 R 4 DATA_PID 0 R 3 OVER WRITE 0 R 2 SETUPT 0 R 1 CPUBUF 0 R 0 reserved - Table 127: DcEndpointStatusImage register: bit description Bit 7 6 5 4 Symbol EPSTAL EPFULL1 EPFULL0 DATA_PID Description This bit indicates whether the endpoint is stalled or not (1 = stalled; 0 = not stalled). Logic 1 indicates that the secondary endpoint buffer is full. Logic 1 indicates that the primary endpoint buffer is full. This bit indicates the data PID of the next packet (0 = DATA0 PID; 1 = DATA1 PID). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 122 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 127: DcEndpointStatusImage register: bit description...continued Bit 3 Symbol OVERWRITE Description This bit is set by hardware. Logic 1 indicates that a new Set-up packet has overwritten the previous set-up information, before it was acknowledged or before the endpoint was stalled. This bit is cleared by reading, if writing the set-up data has finished. Firmware must check this bit before sending an Acknowledge Set-up command or stalling the endpoint. Upon reading logic 1, the firmware must stop ongoing set-up actions and wait for a new Set-up packet. 2 1 0 SETUPT CPUBUF Logic 1 indicates that the buffer contains a Set-up packet. This bit indicates which buffer is currently selected for CPU access (0 = primary buffer; 1 = secondary buffer). reserved 16.2.7 Acknowledge Set-up (F4H) This command acknowledges to the host that a Set-up packet was received. The arrival of a Set-up packet disables the Validate Buffer and Clear Buffer commands for the control IN and OUT endpoints. The microprocessor needs to re-enable these commands by sending an Acknowledge Set-up command, see Section 13.3.6. Code (Hex): F4 -- acknowledge set-up Transaction -- none (code only) 16.3 General commands 16.3.1 Read Endpoint Error Code (R: A0H-AFH) This command returns the status of the last transaction of the selected endpoint, as stored in the DcErrorCode register. Each new transaction overwrites the previous status information. The bit allocation of the DcErrorCode register is shown in Table 128. Code (Hex): A0 to AF -- read error code (control OUT, control IN, endpoint 1 to 14) Transaction -- read 1 byte (code or data) Table 128: DcErrorCode register: bit allocation Bit Symbol Reset Access 7 UNREAD 0 R 6 DATA01 0 R 5 reserved 0 R 0 R 4 3 ERROR[3:0] 0 R 0 R 2 1 0 RTOK 0 R Table 129: DcErrorCode register: bit description Bit 7 6 Symbol UNREAD DATA01 Description Logic 1 indicates that a new event occurred before the previous status was read. This bit indicates the PID type of the last successfully received or transmitted packet (0 = DATA0 PID; 1 = DATA1 PID). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 123 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 129: DcErrorCode register: bit description...continued Bit 5 4 to 1 0 Symbol ERROR[3:0] RTOK Description reserved Error code. For error description, see Table 130. Logic 1 indicates that data was successfully received or transmitted. Table 130: Transaction error codes Error code (Binary) 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Description no error PID encoding error; bits 7 to 4 are not the inverse of bits 3 to 0 PID unknown; encoding is valid, but PID does not exist unexpected packet; packet is not of the expected type (token, data or acknowledge) or is a SET-UP token to a non-control endpoint token CRC error data CRC error time-out error babble error unexpected end-of-packet sent or received NAK (Not AcKnowledge) sent Stall; a token was received, but the endpoint was stalled overflow; the received packet was larger than the available buffer space sent empty packet (ISO only) bit stuffing error sync error wrong (unexpected) toggle bit in DATA PID; data was ignored 16.3.2 Unlock Device (B0H) This command unlocks the DC from write-protection mode after a `resume'. In the `suspend' state, all registers and buffer memory are write-protected to prevent data corruption by external devices during a `resume'. Also, the register access for reading is possible only after the `unlock device' command is executed. After waking up from the `suspend' state, the firmware must unlock the registers and buffer memory by using this command, by writing the unlock code (AA37H) into the DcLock register (8-bit bus: lower byte first). The bit allocation of the DcLock register is given in Table 131. Code (Hex): B0 -- unlock the device Transaction -- write 2 bytes (unlock code) (code or data) Table 131: DcLock register: bit allocation Bit Symbol Reset Access 9397 750 12337 15 1 W 14 0 W 13 1 W 12 0 W 11 1 W 10 0 W 9 1 W 8 0 W 124 of 150 UNLOCK[15:8] = AAH (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 Philips Semiconductors ISP1362 Single-chip USB OTG controller 5 1 W 4 1 W 3 0 W 2 1 W 1 1 W 0 1 W Bit Symbol Reset Access 7 0 W 6 0 W UNLOCK[7:0] = 37H Table 132: DcLock register: bit description Bit 15 to 0 Symbol UNLOCK[15:0] Description Sending data AA37H unlocks the internal registers and buffer memory for writing, following a `resume'. 16.3.3 DcScratch register (R/W: B3H/B2H) This command accesses the 16-bit DcScratch register, which can be used by the firmware to save and restore information. For example, the device status before powering down in the `suspend' state. The register bit allocation is given in Table 133. Code (Hex): B2/B3 -- write or read DcScratch register Transaction -- write or read 2 bytes (code or data) Table 133: DcScratch Information register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 0 R/W 0 R/W 0 R/W 0 R/W 7 15 14 reserved 6 5 0 R/W 4 SFIR[7:0] 0 R/W 0 R/W 0 R/W 0 R/W 0 R/W 3 13 12 11 10 SFIR[12:8] 0 R/W 2 0 R/W 1 0 R/W 0 9 8 Table 134: DcScratch Information register: bit description Bit 15 to 13 12 to 0 Symbol SFIR[12:0] Description reserved; must be logic 0 Scratch Information register 16.3.4 DcFrameNumber register (R: B4H) This command returns the frame number of the last successfully received SOF. It is followed by reading one word from the DcFrameNumber register, containing the frame number. The DcFrameNumber register is shown in Table 135. Remark: After a bus reset, the value of the DcFrameNumber register is undefined. Code (Hex): B4 -- read frame number Transaction -- read 1 or 2 bytes (code or data) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 125 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 135: DcFrameNumber register: bit allocation Bit Symbol Reset [1] Access Bit Symbol Reset [1] Access [1] 15 7 0 R 14 6 0 R 13 reserved 5 0 R 12 4 SOFR[7:0] 0 R 11 3 0 R 10 0 R 2 0 R 9 SOFR[9:8] 0 R 1 0 R 8 0 R 0 0 R Reset value undefined after a bus reset. Table 136: DcFrameNumber register: bit description Bit 15 to 11 10 to 0 Symbol SOFR[9:0] Description reserved frame number Table 137: Example of DcFrameNumber register access A0 HIGH LOW Phase command data Bus lines D[15:8] D[7:0] D[15:0] Word # 0 Description ignored command code (B4H) frame number 16.3.5 DcChipID (R: B5H) This command reads the chip identification code and hardware version number. The firmware must check this information to determine the supported functions and features. This command accesses the DcChipID register, which is shown in Table 138. Code (Hex): B5 -- read chip ID Transaction -- read 2 bytes (code or data) Table 138: DcChipID register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access 0 R 0 R 1 R 0 R 7 0 R 6 1 R 5 15 14 13 12 1 R 4 1 R 11 0 R 3 0 R 10 1 R 2 0 R 9 1 R 1 0 R 8 0 R 0 0 R CHIPIDH[7:0] CHIPIDL[7:0] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 126 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 139: DcChipID register: bit description Bit 15 to 8 7 to 0 Symbol CHIPIDH[7:0] CHIPIDL[7:0] Description chip ID code (36H) silicon version (30H, with 30 representing the BCD encoded version number) 16.3.6 DcInterrupt register (R: C0H) This command indicates the sources of interrupts as stored in the 4-byte DcInterrupt register. Each individual endpoint has its own interrupt bit. The bit allocation of the DcInterrupt register is shown in Table 140. Bit BUSTATUS is used to verify the current bus status in the interrupt service routine. Interrupts are enabled using the DcInterruptEnable register, see Section 16.1.5. While reading the DcInterrupt register, it is recommended that both 2-byte words are read completely. Code (Hex): C0 -- read DcInterrupt register Transaction -- read 4 bytes (code or data) Table 140: DcInterrupt register: bit allocation Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access Bit Symbol Reset Access 23 EP14 0 R 15 EP6 0 R 7 BUSTATUS 0 R 22 EP13 0 R 14 EP5 0 R 6 SP_EOT 0 R 21 EP12 0 R 13 EP4 0 R 5 PSOF 0 R 20 EP11 0 R 12 EP3 0 R 4 SOF 0 R 31 30 29 28 reserved 19 EP10 0 R 11 EP2 0 R 3 EOT 0 R 18 EP9 0 R 10 EP1 0 R 2 SUSPND 0 R 17 EP8 0 R 9 EP0IN 0 R 1 RESUME 0 R 16 EP7 0 R 8 EP0OUT 0 R 0 RESET 0 R 27 26 25 24 Table 141: DcInterrupt register: bit description Bit 31 to 24 23 to 10 9 8 7 6 Symbol EP14 to EP1 EP0IN EP0OUT BUSTATUS SP_EOT Description reserved Logic 1 indicates the interrupt source(s): endpoint 14 to 1. Logic 1 indicates the interrupt source: control IN endpoint. Logic 1 indicates the interrupt source: control OUT endpoint. Monitors the current USB bus status (0 = awake, 1 = suspend). Logic 1 indicates that an EOT interrupt has occurred for a short period. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 Product data Rev. 03 -- 06 January 2004 127 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 141: DcInterrupt register: bit description...continued Bit 5 Symbol PSOF Description Logic 1 indicates that an interrupt is issued every 1 ms because of the Pseudo SOF; after three missed SOFs, the `suspend' state is entered. Logic 1 indicates that an SOF condition was detected. Logic 1 indicates that an internal EOT condition was generated by the DMA Counter reaching zero. Logic 1 indicates that an `awake' to `suspend' change of state was detected on the USB bus. Logic 1 indicates that a `resume' state was detected. Logic 1 indicates that a bus reset condition was detected. 4 3 2 1 0 SOF EOT SUSPND RESUME RESET 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 128 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 17. Limiting values Table 142: Absolute maximum ratings In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol VCC VI Ilu Vesd Tstg [1] Parameter supply voltage input voltage latch-up current electrostatic discharge voltage storage temperature Conditions Min -0.5 -0.5 Max +4.6 +6.0 100 +2000 +150 Unit V V mA V C VI < 0 or VI > VCC ILI < 1 A [1] -2000 -60 Equivalent to discharging a 100 pF capacitor through a 1.5 k resistor (Human Body Model). 18. Recommended operating conditions Table 143: Recommended operating conditions DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. Symbol VCC VI Parameter supply voltage input voltage on digital I/O lines 1.8 V tolerant pins 3.3 V tolerant pins 5 V tolerant pins VI(AI/O) VO(od) Tamb input voltage on analog I/O lines (pins DP and DM) open-drain output pull-up voltage ambient temperature 5 V tolerant pins non 5 V tolerant pins Conditions Min 3.0 0 0 0 0 0 0 -40 Typ 3.3 1.8 3.3 5.0 Max 3.6 2.0 3.6 5.5 3.6 5.5 3.6 +85 Unit V V V V V V V C 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 129 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 19. Static characteristics Table 144: Static characteristics: supply pins VCC = 3.3 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol ICC(HC) ICC(DC) ICC(HC+DC) ICC(susp) Parameter Conditions Min HC and DC are suspended [1] Typ 33 20 50 60 Max - Unit mA mA mA A operating supply current for the DC suspended HC operating supply current for the HC suspended DC operating supply current for the host and the device suspend supply current - [1] Power consumption on the charge pump is not included. Table 145: Static characteristics: digital pins VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Input levels VIL VIH Vth(LH) Vth(HL) Vhys Output levels VOL VOH LOW-level output voltage HIGH-level output voltage IOL = 4 mA IOL = 20 A IOH = 4 mA IOH = 20 A Leakage current ILI CIN IOZ [1] [2] [1] Parameter LOW-level input voltage HIGH-level input voltage positive-going threshold voltage negative-going threshold voltage hysteresis voltage Conditions Min 2.0 1.4 0.9 0.4 2.4 VCC - 0.1 [2] Typ - Max 0.8 1.9 1.5 0.7 0.4 0.1 +5 5 +5 Unit V V V V V V V V V A pF A Schmitt-trigger inputs input leakage current pin capacitance OFF-state output current pin to GND -5 -5 Open-drain outputs Not applicable for open-drain outputs. These values are applicable to transistor inputs. The value will be different if internal pull-up or pull-down resistors are used. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 130 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 146: Static characteristics: analog I/O pins (D+, D-)[1] VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Input levels VDI VCM VIL VIH Output levels VOL VOH ILZ Capacitance CIN Resistance Rpd(OTG) Rpd(H) Rpu(OTG) ZDRV ZINP Termination VTERM termination voltage for upstream port pull up (RPU) [3] Parameter differential input sensitivity differential common mode voltage LOW-level input voltage HIGH-level input voltage LOW-level output voltage HIGH-level output voltage OFF-state leakage current transceiver capacitance Conditions |VI(D+) - VI(D-)| includes VDI range Min 0.2 0.8 2.0 Typ - Max 2.5 0.8 0.3 3.6 +10 10 24.8 20 1575 3090 44 3.6 Unit V V V V V V A pF k k M V RL = 1.5 k to +3.6 V RL = 15 k to GND 2.8 -10 Leakage current pin to GND 14.25 10 900 1425 [2] pull-down resistance on enable internal pins OTG_DP1 and OTG_DM1 resistors pull-down resistance on pins H_DP2 and H_DM2 pull-up resistance on OTG_DP1 driver output impedance input impedance enable internal resistors bus idle bus driven steady-state drive 29 10 3.0 [1] [2] [3] DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. D+ is the USB positive data line and D- is the USB negative data line. Includes external resistors of 18 10% on H_DP2 and H_DM2, and 27 10% on OTG_DP1 and OTG_DM1. In the suspend mode, the minimum voltage is 2.7 V. Table 147: Static characteristics: charge pump VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; CLOAD = 2 F; unless otherwise specified. Symbol VBUS ILOAD Parameter regulated VBUS voltage maximum load current Conditions ILOAD = 8 mA from VBUS(OTG); see Figure 29 external capacitor of 27 nF; VCC = 3.0 V to 3.6 V external capacitor of 82 nF; VCC = 3.0 V to 3.3 V external capacitor of 82 nF; VCC = 3.3 V to 3.6 V CLOAD VBUS(LEAK) 9397 750 12337 Min 1 Typ 5 - Max 5.25 8 14 20 6.5 0.2 Unit V mA mA mA F V 131 of 150 output capacitance VBUS(OTG) leakage voltage VBUS(OTG) not driven Rev. 03 -- 06 January 2004 - (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 147: Static characteristics: charge pump...continued VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; CLOAD = 2 F; unless otherwise specified. Symbol ICC(cp)(susp) Parameter suspend supply current for charge pump Conditions GlobalPowerDown bit of the HcHardwareConfiguration register is logic 0 GlobalPowerDown bit of the HcHardwareConfiguration register is logic 1 ICC(cp) operating supply current in charge pump mode ATX is idle ILOAD = 8 mA ILOAD = 0 mA Vth(VBUS_VLD) Vth(SESS_END) Vhys(SESS_END) Vth(ASESS_VLD) Vhys(ASESS_VLD) Vth(BSESS_VLD) Vhys(BSESS_VLD) E IVBUS(leak) RVBUS(PU) RVBUS(PD) RVBUS(IDLE) RVBUS(ACTIVE) VBUS valid threshold VBUS session end threshold VBUS session end hysteresis VBUS A valid threshold VBUS A valid hysteresis VBUS B valid threshold VBUS B valid hysteresis efficiency when loaded leakage current from VBUS VBUS pull-up resistance VBUS pull-down resistance VBUS idle impedance for the A-device VBUS active pull-down impedance pull to VCC when enabled pull to GND when enabled when ID = LOW and DRV_VBUS = 0 when ID = HIGH and DRV_VBUS =1 ILOAD = 8 mA; VIN = 3 V; see Figure 28 4.4 0.2 0.8 2 281 656 40 150 200 200 75 15 350 20 300 0.8 2 4 100 mA A V V mV V mV V mV % A k k Min Typ Max 45 Unit A - - 15 A 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 132 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 100 E efficiency (%) 80 004aaa211 60 40 20 VCC = 3.0 V VCC = 3.3 V VCC = 3.6 V 0 0 5 10 15 20 ILOAD (mA) 25 82 nF charge pump capacitor. Fig 28. Efficiency versus load current. 004aaa212 5.3 VBUS (V) 5.2 5.1 5.0 4.9 4.8 VCC = 3.0 V 4.7 VCC = 3.3 V VCC = 3.6 V 4.6 0 5 10 15 20 ILOAD (mA) 25 82 nF charge pump capacitor. Fig 29. Output voltage versus load current. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 133 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 20. Dynamic characteristics Table 148: Dynamic characteristics VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; unless otherwise specified. Symbol Reset tW(RESET) pulse width on input RESET crystal oscillator running crystal oscillator stopped Crystal oscillator fXTAL RS CLOAD J tDUTY tCR, tCF [1] [2] [1] Parameter Conditions Min 10 - Typ - Max - Unit ms ms crystal frequency series resistance load capacitance external clock jitter clock duty cycle rise time and fall time CX1, CX2 = 22 pF [2] 45 - 12 12 50 - 100 500 55 3 MHz pF ps % ns External clock input Dependent on the crystal oscillator start-up time. Tolerance of the clock frequency is 50 ppm. Table 149: Dynamic characteristics: analog I/O lines (D+, D-)[1] VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; CL = 50 pF; RPU = 1.5 k 5 % on DP to VTERM; unless otherwise specified. Symbol tFR Parameter rise time Conditions CL = 50 pF; 10% to 90% of |VOH - VOL| CL = 50 pF; 90% to 10% of |VOH - VOL| [2] Min 4 Typ - Max 20 Unit ns Driver characteristics tFF fall time 4 - 20 ns FRFM VCRS [1] [2] [3] differential rise/fall time matching (tFR/tFF) output signal crossover voltage 90 1.3 - 111.11 2.0 % V [2][3] DP represents OTG_DP1 and H_DP2, and DM represents OTG_DM1 and H_DM2. Test circuit. Excluding the first transition from the idle state. Characterized only, not tested. Limits guaranteed by design. Table 150: Dynamic characteristics: charge pump VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; CLOAD = 2 F; unless otherwise specified. Symbol tSTART-UP tCOMP_CLK Parameter rise time to VBUS = 4.4 V clock period Conditions ILOAD = 8 mA; CLOAD = 10 F Min 1.5 Typ Max 100 3 Unit ms s Driver characteristics 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 134 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Table 150: Dynamic characteristics: charge pump...continued VCC = 3.0 V to 3.6 V; GND = 0 V; Tamb = -40 C to +85 C; CLOAD = 2 F; unless otherwise specified. Symbol tVBUS(VALID_dly) tVBUS(PULSE) tVBUS(VALID_dly) VRIPPLE Parameter minimum time VBUS(VALID) error VBUS pulsing time VBUS pull-down time output ripple with constant load ILOAD = 8 mA Conditions Min 100 10 50 Typ Max 200 30 50 Unit s ms ms mV 20.1 Programmed I/O timing * If you are accessing only the HC, then the HC programmed I/O timing applies. * If you are accessing only the DC, then the DC programmed I/O timing applies. * If you are accessing both the HC and the DC, then the DC programmed I/O timing applies. 20.1.1 HC Programmed I/O timing Table 151: Dynamic characteristics: HC Programmed interface timing Symbol tAS tAH Read timing tSHSL_R tSHSL_B tSLRL tRHSH tRL tRHRL TRC tRHDZ tRLDV Write timing tWL tWHWL TWC tSLWL tWHSH tWDSU tWDH WR LOW pulse width WR HIGH to next WR LOW WR cycle CS LOW to WR LOW WR HIGH to CS HIGH WR data set-up time WR data hold time 26 110 136 0 0 3 4 ns ns ns ns ns ns ns first RD/WR after command (A0 = HIGH) first RD/WR after command (A0 = HIGH) CS LOW to RD LOW RD HIGH to CS HIGH RD LOW pulse width RD HIGH to next RD LOW RD cycle RD data hold time RD LOW to data valid register access buffer access 300 462 0 0 33 110 143 3 22 ns ns ns ns ns ns ns ns ns Parameter address set-up time before CS address hold time after CS Conditions Min 5 2 Typ Max Unit ns ns 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 135 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller CS t SHSL A0 t RLRH t SLRL t SLWL t RHSH t RHRL T RC RD t RLDV D [15:0] tAS t AH data valid t WL data valid t WHWL TWC data valid data valid t WHSH t RHDZ WR t WDH D [15:0] data valid data valid data valid t WDSU data valid data valid MGT969 Fig 30. HC Programmed interface timing. 20.1.2 DC Programmed I/O timing Table 152: Dynamic characteristics: DC Programmed interface timing Symbol tRHAX tAVRL tSHDZ tRHSH tRLRH tRLDV tSHRL + tRLRH + tRHSH tWHAX tAVWL tSHWL + tWLWH + tWHSH tWLWH tWHSH tDVWH tWHDZ [1] Parameter address hold time after RD HIGH address set-up time before RD LOW data outputs high-impedance time after CS HIGH chip deselect time after RD HIGH RD pulse width data valid time after RD LOW read cycle time address hold time after WR HIGH address set-up time before WR LOW write cycle time WR pulse width chip deselect time after WR HIGH data set-up time before WR HIGH data hold time after WR HIGH Conditions Min 3 0 0 25 180 3 0 [1] Typ - Max 3 22 - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns Read timing (see Figure 31) Write timing (see Figure 32) 180 22 0 5 3 In the command to data phase, the minimum value of the write command to the read data or write data cycle time should be 205 ns. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 Product data Rev. 03 -- 06 January 2004 136 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller t RHAX A0 tAVRL t SHDZ CS/DACK2(2) t RLRH RD t RLDV D[15:0] 004aaa105 t SHRL(1) t RHSH (1) For tSHRL both CS and RD must be deasserted. (2) Programmable polarity: shown as active LOW. Fig 31. DC Programmed interface read timing (I/O and 8237 compatible DMA). t WHAX A0 tAVWL CS/DACK2(2) t WLWH t SHWL(1) t WHSH WR t DVWH D[15:0] 004aaa106 t WHDZ (1) For tSHWL both CS and WR must be deasserted. (2) Programmable polarity: shown as active LOW. Fig 32. DC Programmed interface write timing (I/O and 8237 compatible DMA). 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 137 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 20.2 DMA timing 20.2.1 HC single-cycle DMA timing Table 153: Dynamic characteristics: HC single-cycle DMA timing Symbol tRL tRLDV tRHDZ tWSU tWHD tAHRH tALRL TDC tSHAH tRHAL tDS [1] Parameter RD pulse width read process data set-up time read process data hold time write process data set-up time write process data hold time DACK1 HIGH to DREQ1 HIGH DACK1 LOW to DREQ1 LOW DREQ1 cycle RD/WR HIGH to DACK1 HIGH DREQ1 HIGH to DACK1 LOW DREQ1 pulse spacing Conditions Min 33 30 0 5 0 72 [1] Typ - Max 21 - Unit ns ns ns ns ns ns ns ns ns ns ns Read/write timing 0 0 146 tRHAL + tDS +tALRL T DC DREQ1 t DS t ALRL t RHAL DACK1 t AHRH t RLDV D [15:0] (read) data valid t RHDZ t SHAH D [15:0] (write) data valid t WSU RD or WR t WHD 004aaa107 Fig 33. HC single-cycle DMA timing. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 138 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 20.2.2 HC burst mode DMA timing Table 154: Dynamic characteristics: HC burst mode DMA timing Symbol Parameter tRL tRHRL TRC tSLRL tSHAH tRHAL TDC tDS(read) tDS(write) WR/RD LOW pulse width WR/RD HIGH to next WR/RD LOW WR/RD cycle RD/WR LOW to DREQ1 LOW RD/WR HIGH to DACK1 HIGH DREQ1 HIGH to DACK1 LOW DREQ1 cycle DREQ1 pulse spacing (read) DREQ1 pulse spacing (write) 4-cycle burst mode 8-cycle burst mode 4-cycle burst mode 8-cycle burst mode [1] tSLAL + (4 or 8)tRC + tDS Conditions Min 42 60 102 22 0 0 [1] Typ - Max 64 - Unit ns ns ns ns ns ns ns ns ns ns ns Read/write timing (for 4-cycle and 8-cycle burst mode) 105 150 72 167 t DS DREQ1 t RHSH t RHAL DACK1 t RHRL t SHAH t SLRL RD or WR 004aaa108 T RC t RLRH Fig 34. HC burst mode DMA timing. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 139 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 20.2.3 DC single-cycle DMA timing (8237 mode) Table 155: Dynamic characteristics: DC single-cycle DMA timing (8237 mode) Symbol tASRP Tcy(DREQ2) Parameter DREQ2 off after DACK2 on cycle time signal DREQ2 Conditions Min 180 Typ Max 40 Unit ns ns T RC t ASRP DREQ2 DACK2(1) 004aaa111 (1) Programmable polarity: shown as active LOW. Fig 35. DC single-cycle DMA timing (8237 mode). 20.2.4 DC single-cycle DMA read timing in DACK-only mode Table 156: Dynamic characteristics: DC single-cycle DMA read timing in DACK-only mode Symbol tASRP tASAP tASAP + tAPRS tASDV tAPDZ Parameter DREQ off after DACK on DACK pulse width DREQ on after DACK off data valid after DACK on data hold after DACK off Conditions Min 25 180 Typ Max 40 22 3 Unit ns ns ns ns ns t ASRP DREQ2 t ASAP DACK2(1) t APRS t ASDV DATA t APDZ 004aaa112 (1) Programmable polarity: shown as active LOW. Fig 36. DC single-cycle DMA read timing in DACK-only mode. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 140 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 20.2.5 DC single-cycle DMA write timing in DACK-only mode Table 157: Dynamic characteristics: DC single-cycle DMA write timing in DACK-only mode Symbol tASRP tASAP tASAP + tAPRS tASDV tAPDZ Parameter DREQ2 off after DACK2 on DACK2 pulse width DREQ2 on after DACK2 off data valid after DACK2 on data hold after DACK2 off Conditions Min 25 180 Typ Max 40 22 3 Unit ns ns ns ns ns t ASAP t ASRP DREQ2 t APRS t ASDV DACK2(1) t APDZ DATA 004aaa113 (1) Programmable polarity: shown as active LOW. Fig 37. DC single-cycle DMA write timing in DACK-only mode. 20.2.6 DC burst mode DMA timing Table 158: Dynamic characteristics: DC burst mode DMA timing Symbol tRSIH tILRP tIHAP tIHIL Parameter input RD/WR HIGH after DREQ on DREQ off after input RD/WR LOW DACK off after input RD/WR HIGH DMA burst repeat interval (input RD/WR HIGH to LOW) tRL or tWL is 30 ns (min) Conditions Min 22 0 160 Typ Max 60 Unit ns ns ns ns 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 141 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller t RSIH DREQ2 t ILRP t IHAP DACK2(1) t IHIL RD or WR 004aaa115 (1) Programmable polarity: shown as active LOW. Fig 38. DC burst mode DMA timing. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 142 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 21. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 10 x 10 x 1.4 mm SOT314-2 c y X A 48 49 33 32 ZE e E HE wM bp 64 1 pin 1 index 16 ZD bp D HD wM B vM B vM A 17 detail X L Lp A A2 A1 (A 3) e 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.6 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 10.1 9.9 E (1) 10.1 9.9 e 0.5 HD HE L 1 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 1.45 1.05 1.45 1.05 7 0o o 12.15 12.15 11.85 11.85 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT314-2 REFERENCES IEC 136E10 JEDEC MS-026 JEITA EUROPEAN PROJECTION ISSUE DATE 00-01-19 03-02-25 Fig 39. LQFP64 package outline. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 143 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 6 x 6 x 0.8 mm SOT543-1 D B A ball A1 index area A E A1 detail X A2 e1 e 1/2 C eb v M w M CAB C y1 C y K J H G F E D C B A ball A1 index area 1 2 3 4 5 6 7 8 9 10 1/2 e e2 e X 0 2.5 scale 5 mm DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.1 A1 0.25 0.15 A2 0.85 0.75 b 0.35 0.25 D 6.1 5.9 E 6.1 5.9 e 0.5 e1 4.5 e2 4.5 v 0.15 w 0.05 y 0.08 y1 0.1 OUTLINE VERSION SOT543-1 REFERENCES IEC --JEDEC MO-195 JEITA --- EUROPEAN PROJECTION ISSUE DATE 00-11-22 02-04-09 Fig 40. TFBGA64 package outline. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 144 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 22. Soldering 22.1 Introduction to soldering surface mount packages This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our Data Handbook IC26; Integrated Circuit Packages (document order number 9398 652 90011). There is no soldering method that is ideal for all IC packages. Wave soldering can still be used for certain surface mount ICs, but it is not suitable for fine pitch SMDs. In these situations reflow soldering is recommended. In these situations reflow soldering is recommended. 22.2 Reflow soldering Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Driven by legislation and environmental forces the worldwide use of lead-free solder pastes is increasing. Several methods exist for reflowing; for example, convection or convection/infrared heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 100 and 200 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 270 C depending on solder paste material. The top-surface temperature of the packages should preferably be kept: * below 225 C (SnPb process) or below 245 C (Pb-free process) - for all BGA, HTSSON..T and SSOP..T packages - for packages with a thickness 2.5 mm - for packages with a thickness < 2.5 mm and a volume 350 mm3 so called thick/large packages. * below 240 C (SnPb process) or below 260 C (Pb-free process) for packages with a thickness < 2.5 mm and a volume < 350 mm3 so called small/thin packages. Moisture sensitivity precautions, as indicated on packing, must be respected at all times. 22.3 Wave soldering Conventional single wave soldering is not recommended for surface mount devices (SMDs) or printed-circuit boards with a high component density, as solder bridging and non-wetting can present major problems. To overcome these problems the double-wave soldering method was specifically developed. If wave soldering is used the following conditions must be observed for optimal results: * Use a double-wave soldering method comprising a turbulent wave with high upward pressure followed by a smooth laminar wave. 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 145 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller * For packages with leads on two sides and a pitch (e): - larger than or equal to 1.27 mm, the footprint longitudinal axis is preferred to be parallel to the transport direction of the printed-circuit board; - smaller than 1.27 mm, the footprint longitudinal axis must be parallel to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves at the downstream end. * For packages with leads on four sides, the footprint must be placed at a 45 angle to the transport direction of the printed-circuit board. The footprint must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Typical dwell time of the leads in the wave ranges from 3 to 4 seconds at 250 C or 265 C, depending on solder material applied, SnPb or Pb-free respectively. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. 22.4 Manual soldering Fix the component by first soldering two diagonally-opposite end leads. Use a low voltage (24 V or less) soldering iron applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C. 22.5 Package related soldering information Table 159: Suitability of surface mount IC packages for wave and reflow soldering methods Package[1] BGA, HTSSON..T[3], LBGA, LFBGA, SQFP, SSOP..T[3], TFBGA, USON, VFBGA Soldering method Wave not suitable Reflow[2] suitable suitable DHVQFN, HBCC, HBGA, HLQFP, HSO, HSOP, not suitable[4] HSQFP, HSSON, HTQFP, HTSSOP, HVQFN, HVSON, SMS PLCC[5], SO, SOJ LQFP, QFP, TQFP SSOP, TSSOP, VSO, VSSOP CWQCCN..L[8], [1] [2] suitable not WQCCN..L[8] recommended[5][6] not recommended[7] not suitable suitable suitable suitable not suitable PMFP[9], For more detailed information on the BGA packages refer to the (LF)BGA Application Note (AN01026); order a copy from your Philips Semiconductors sales office. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum temperature (with respect to time) and body size of the package, there is a risk that internal or external package cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the Drypack information in the Data Handbook IC26; Integrated Circuit Packages; Section: Packing Methods. (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. 9397 750 12337 Product data Rev. 03 -- 06 January 2004 146 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller These transparent plastic packages are extremely sensitive to reflow soldering conditions and must on no account be processed through more than one soldering cycle or subjected to infrared reflow soldering with peak temperature exceeding 217 C 10 C measured in the atmosphere of the reflow oven. The package body peak temperature must be kept as low as possible. These packages are not suitable for wave soldering. On versions with the heatsink on the bottom side, the solder cannot penetrate between the printed-circuit board and the heatsink. On versions with the heatsink on the top side, the solder might be deposited on the heatsink surface. If wave soldering is considered, then the package must be placed at a 45 angle to the solder wave direction. The package footprint must incorporate solder thieves downstream and at the side corners. Wave soldering is suitable for LQFP, QFP and TQFP packages with a pitch (e) larger than 0.8 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm. Wave soldering is suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm. Image sensor packages in principle should not be soldered. They are mounted in sockets or delivered pre-mounted on flex foil. However, the image sensor package can be mounted by the client on a flex foil by using a hot bar soldering process. The appropriate soldering profile can be provided on request. Hot bar soldering or manual soldering is suitable for PMFP packages. [3] [4] [5] [6] [7] [8] [9] 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 147 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 23. Revision history Table 160: Revision history Rev Date 03 20040106 CPCN Description Product data (9397 750 12337) Modifications: * * * * * * * * * * * * * * * * * * * * * * * * * 02 01 20030219 20021120 - Added the OTG logo. Changed reference to OTG specification from Rev.1.0 to Rev. 1.0a Table 1 and Figure 3: added type number ISP1362EE/01. Figure 1: updated. Figure 3: added index area. Table 2: updated. Section 9.7.1: updated. Section 10: added. Section 11.4.1: changed 3 ms to 5 ms in list item 2. Section 11.6: added a remark. Section 12.2: updated list item 5. Section 12.3: updated. Section 12.5.1: updated. Section 12.8: updated. Section 13.5.1: updated Table 23: updated. Table 33: updated. Table 72: changed symbol to CHIPID. Table 76: updated. Table 143: updated. Table 145: changed minimum value of VOH to VCC. Table 146: updated Rpd and Rpu. Table 147: changed various symbols. Table 152: changed symbols of read and write cycle time. Deleted table on timing symbols (old Section 18.1). Product data (9397 750 10767) Preliminary data (9397 750 10087) 9397 750 12337 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 148 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller 24. Data sheet status Level I II Data sheet status[1] Objective data Preliminary data Product status[2][3] Development Qualification Definition This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). III Product data Production [1] [2] [3] Please consult the most recently issued data sheet before initiating or completing a design. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com. For data sheets describing multiple type numbers, the highest-level product status determines the data sheet status. 25. Definitions Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. Right to make changes -- Philips Semiconductors reserves the right to make changes in the products - including circuits, standard cells, and/or software - described or contained herein in order to improve design and/or performance. When the product is in full production (status `Production'), relevant changes will be communicated via a Customer Product/Process Change Notification (CPCN). Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. 27. Trademarks ARM -- is a trademark of ARM Ltd. DragonBall -- is a trademark of Motorola, Inc. Fujitsu -- is a registered trademark of Fujitsu Corp. GoodLink -- is a trademark of Koninklijke Philips Electronics N.V. Hitachi -- is a registered trademark of Hitachi Ltd. Intel -- is a registered trademark of Intel Corp. Motorola -- is a registered trademark of Motorola, Inc. NEC -- is a registered trademark of NEC Corp. PowerPC -- is a trademark of IBM Corp. SoftConnect -- is a trademark of Koninklijke Philips Electronics N.V. SPARClite -- is a registered trademark of Sparc International. StrongARM -- is a trademark of ARM Ltd. Toshiba -- is a registered trademark of Toshiba Corp. 26. Disclaimers Life support -- These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Contact information For additional information, please visit http://www.semiconductors.philips.com. For sales office addresses, send e-mail to: sales.addresses@www.semiconductors.philips.com. 9397 750 12337 Fax: +31 40 27 24825 (c) Koninklijke Philips Electronics N.V. 2004. All rights reserved. Product data Rev. 03 -- 06 January 2004 149 of 150 Philips Semiconductors ISP1362 Single-chip USB OTG controller Contents 1 2 3 3.1 4 5 6 7 7.1 7.2 8 8.1 8.2 8.3 8.4 8.5 8.6 8.7 8.8 8.9 8.10 9 9.1 9.2 9.3 9.4 9.5 9.6 9.7 10 11 11.1 11.2 11.3 11.4 11.5 11.6 12 12.1 12.2 12.3 12.4 12.5 12.6 12.7 12.8 12.9 13 13.1 13.2 13.3 General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Host/peripheral roles . . . . . . . . . . . . . . . . . . . . . . . . . 3 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Functional description . . . . . . . . . . . . . . . . . . . . . . . 13 On-The-Go (OTG) controller . . . . . . . . . . . . . . . . . . 13 Advanced Philips Slave Host Controller (PSHC) . . . 13 Philips Device Controller (DC) . . . . . . . . . . . . . . . . . 13 Phase-Locked Loop (PLL) clock multiplier . . . . . . . . 13 USB and OTG transceivers . . . . . . . . . . . . . . . . . . . 13 Overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . 13 Bus interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 DC and HC buffer memory. . . . . . . . . . . . . . . . . . . . 13 GoodLink . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Host and device bus interface . . . . . . . . . . . . . . . . . 14 Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 15 PIO access mode. . . . . . . . . . . . . . . . . . . . . . . . . . . 19 DMA mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 PIO access to internal control registers . . . . . . . . . . 21 PIO access to the buffer memory. . . . . . . . . . . . . . . 24 Setting up a DMA transfer . . . . . . . . . . . . . . . . . . . . 26 Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Power-on reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . 30 On-The-Go (OTG) controller . . . . . . . . . . . . . . . . . . . 31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Dual-role device . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Session Request Protocol (SRP) . . . . . . . . . . . . . . . 33 Host Negotiation Protocol (HNP) . . . . . . . . . . . . . . . 34 Power saving in the idle state and during wake-up . 38 Current capacity of the OTG charge pump . . . . . . . 38 USB Host Controller (HC) . . . . . . . . . . . . . . . . . . . . . 39 USB states of the HC . . . . . . . . . . . . . . . . . . . . . . . . 39 USB traffic generation . . . . . . . . . . . . . . . . . . . . . . . 40 USB ports. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Philips Transfer Descriptor (PTD). . . . . . . . . . . . . . . 41 Features of the control and bulk transfer (aperiodic transfer) . . . . . . . . . . . . . . . . . . . . . . . . . 44 Features of the interrupt transfer . . . . . . . . . . . . . . . 46 Features of the isochronous (ISO) transfer . . . . . . . 46 Overcurrent protection circuit . . . . . . . . . . . . . . . . . . 46 ISP1362 HC Power Management . . . . . . . . . . . . . . 49 USB Device Controller (DC) . . . . . . . . . . . . . . . . . . . 50 DC data transfer operation . . . . . . . . . . . . . . . . . . . . 50 Device DMA transfer . . . . . . . . . . . . . . . . . . . . . . . . 51 Endpoint description . . . . . . . . . . . . . . . . . . . . . . . . 52 13.4 13.5 14 14.1 14.2 14.3 14.4 14.5 14.6 15 15.1 15.2 15.3 15.4 15.5 15.6 15.7 15.8 15.9 16 16.1 16.2 16.3 17 18 19 20 20.1 20.2 21 22 22.1 22.2 22.3 22.4 22.5 23 24 25 26 27 DC direct memory access (DMA) transfer . . . . . . . . 54 ISP1362 DC suspend and resume . . . . . . . . . . . . . . 58 OTG registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 OtgControl register (R/W: 62H/E2H) . . . . . . . . . . . . 60 OtgStatus register (R: 67H) . . . . . . . . . . . . . . . . . . . 62 OtgInterrupt register (R/W: 68H/E8H). . . . . . . . . . . . 63 OtgInterruptEnable register (R/W: 69H/E9H) . . . . . . 66 OtgTimer register (R/W: 6AH/EAH) . . . . . . . . . . . . . 67 OtgAltTimer register (R/W: 6CH/ECH) . . . . . . . . . . . 68 HC registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 HC control and status registers . . . . . . . . . . . . . . . . 71 HC Frame Counter registers. . . . . . . . . . . . . . . . . . . 78 HC Root Hub registers . . . . . . . . . . . . . . . . . . . . . . . 82 HC DMA and interrupt control registers . . . . . . . . . . 92 HC miscellaneous registers . . . . . . . . . . . . . . . . . . . 98 HC buffer RAM control registers . . . . . . . . . . . . . . . . 99 Isochronous (ISO) transfer registers. . . . . . . . . . . . 101 Interrupt transfer registers. . . . . . . . . . . . . . . . . . . . 103 Control and bulk transfer (aperiodic transfer) registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 Device Controller (DC) registers . . . . . . . . . . . . . . . 110 Initialization commands . . . . . . . . . . . . . . . . . . . . . 113 Data flow commands . . . . . . . . . . . . . . . . . . . . . . . 119 General commands . . . . . . . . . . . . . . . . . . . . . . . . 123 Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129 Recommended operating conditions . . . . . . . . . . . 129 Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . 130 Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . 134 Programmed I/O timing. . . . . . . . . . . . . . . . . . . . . . 135 DMA timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138 Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143 Soldering. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Introduction to soldering surface mount packages . 145 Reflow soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Wave soldering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 145 Manual soldering . . . . . . . . . . . . . . . . . . . . . . . . . . 146 Package related soldering information . . . . . . . . . . 146 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . 148 Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 Trademarks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 (c) Koninklijke Philips Electronics N.V. 2004. Printed in The Netherlands All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. Date of release: 06 January 2004 Document order number: 9397 750 12337 |
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